 | 2011 |
|---|
| 8 |       | Shibaji Banerjee,
Jimson Mathew,
Dhiraj K. Pradhan,
Bhargab B. Bhattacharya,
Saraju P. Mohanty:
A Routing-Aware ILS Design Technique.
IEEE Trans. VLSI Syst. 19(12): 2335-2338 (2011) |
| 7 | | Shibaji Banerjee,
Jimson Mathew,
Saraju P. Mohanty,
Dhiraj K. Pradhan,
Maciej J. Ciesielski:
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
J. Low Power Electronics 7(4): 471-481 (2011) |
| 2007 |
|---|
| 6 | | Shibaji Banerjee,
Dipanwita Roy Chowdhury,
Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1331-1339 (2007) |
| 2006 |
|---|
| 5 | | Shibaji Banerjee,
Dipanwita Roy Chowdhury:
Built-In Self-Test for Flash Memory Embedded in SoC.
DELTA 2006: 379-384 |
| 4 | | Shibaji Banerjee,
Dipanwita Roy Chowdhury,
Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set.
VLSI Design 2006: 175-180 |
| 3 | | Shibaji Banerjee,
Debdeep Mukhopadhyay,
C. V. G. Rao,
Dipanwita Roy Chowdhury:
An integrated DFT solution for mixed-signal SOCs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1368-1377 (2006) |
| 2005 |
|---|
| 2 | | Debdeep Mukhopadhyay,
Shibaji Banerjee,
Dipanwita Roy Chowdhury,
Bhargab B. Bhattacharya:
CryptoScan: A Secured Scan Chain Architecture.
Asian Test Symposium 2005: 348-353 |
| 1 | | Shibaji Banerjee,
Debdeep Mukhopadhyay,
Dipanwita Roy Chowdhury:
Computer Aided Test (CAT) Tool for Mixed Signal SOCs.
VLSI Design 2005: 787-790 |
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