Poras T. Balsara

	2012
54		Sujan K. Manohar, Vinod K. Somasundar, Ramakrishnan Venkatasubramanian, Poras T. Balsara: Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management. VLSI Design 2012: 125-130
53		Sujan K. Manohar, Ramakrishnan Venkatasubramanian, Poras T. Balsara: Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency. VLSI Design 2012: 221-226
	2011
52		Ioannis L. Syllaios, Poras T. Balsara: Multi-clock domain analysis and modeling of all-digital frequency synthesizers. ISCAS 2011: 153-156
51		Imran Bashir, Robert Bogdan Staszewski, Oren Eliezer, Bhaskar Banerjee, Poras T. Balsara: A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. J. Solid-State Circuits 46(2): 403-415 (2011)
	2010
50		Mangesh K. Kunchamwar, Durga P. Prasad, Pawan Hegde, Poras T. Balsara, Rama Sangireddy: Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding. ICPP Workshops 2010: 34-43
49		Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija: Design of a link-controller architecture for multiple serial link protocols. SoCC 2010: 266-271
48		Venkata K. Kidambi Srinivasan, Chitranjan K. Singh, Poras T. Balsara: A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder. IEEE Trans. VLSI Syst. 18(9): 1372-1376 (2010)
47		Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski: Recombination of Envelope and Phase Paths in Wideband Polar Transmitters. IEEE Trans. on Circuits and Systems 57-I(8): 1891-1904 (2010)
46		Jaimin Mehta, Vasile Zoicas, Oren Eliezer, Robert Bogdan Staszewski, Sameh Rezeq, Mitch Entezari, Poras T. Balsara: An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter. IEEE Trans. on Circuits and Systems 57-II(3): 193-197 (2010)
	2009
45		Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer: All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters. IEEE Trans. on Circuits and Systems 56-I(11): 2487-2497 (2009)
44		Imtinan Elahi, Khurram Muhammad, Poras T. Balsara: Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation. IEEE Trans. on Circuits and Systems 56-II(1): 86-90 (2009)
	2008
43		Ioannis L. Syllaios, Robert Bogdan Staszewski, Poras T. Balsara: Time-Domain Modeling of an RF All-Digital PLL. IEEE Trans. on Circuits and Systems 55-II(6): 601-605 (2008)
	2007
42		Chitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara: Effect of Word-length Precision on the Performance of MIMO Systems. ISCAS 2007: 2598-2601
41		Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta: A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters. ISCAS 2007: 3275-3278
40		Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta: A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters. ISCAS 2007: 3279-3282
39		Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara: VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. VLSI Design 2007: 836-841
38		Raghunath Cherukuri, Poras T. Balsara: Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels. VTC Fall 2007: 2070-2074
	2006
37		Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara: Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC 2006: 287-298
36		Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara: Reconfigurable CAM Architecture for Network Search Engines. ICCD 2006
35		Ioannis L. Syllaios, Poras T. Balsara, Oren E. Eliezer: A generalized signal reconstruction method for designing interpolation filters. ISCAS 2006
34		V. Ramakrishnan, Poras T. Balsara: A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. VLSI Design 2006: 197-202
33		Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara: Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design 2006: 754-757
	2005
32		Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia: Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC 2005: 651-656
31		Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara: FPGA Architecture for Standby Power Management. FPT 2005: 181-188
30		Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara: Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. ICCD 2005: 243-248
29		Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara: Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS 2005
28		Robert B. Staszewski, Roman Staszewski, Poras T. Balsara: VHDL Simulation and Modeling of an All-Digital RF Transmitter. IWSOC 2005: 233-238
27		N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell: The Impact of Inductance on Transients Affecting Gate Oxide Reliability. VLSI Design 2005: 709-713
26		Ramaprasath Vilangudipitchai, Poras T. Balsara: Power Switch Network Design for MTCMOS. VLSI Design 2005: 836-839
25		Robert B. Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara: SoC with an integrated DSP and a 2.4-GHz RF transmitter. IEEE Trans. VLSI Syst. 13(11): 1253-1265 (2005)
	2004
24		Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara: PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. ICCD 2004: 6-11
23		Robert B. Staszewski, Chan Fernando, Poras T. Balsara: Event-driven simulation and modeling of an RF oscillator. ISCAS (4) 2004: 641-644
22		N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara: Interconnect Modeling for Copper/Low-k Technologies. VLSI Design 2004: 425-
	2003
21		N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell: Benchmarks for Interconnect Parasitic Resistance and Capacitance. ISQED 2003: 163-
	2002
20		N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell: Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. VLSI Design 2002: 141
	2001
19		Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara: Challenges in integrated CMOS transceivers for short distance wireless. ACM Great Lakes Symposium on VLSI 2001: 45-50
18		Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell: Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. VLSI Design 2001: 365-370
17		Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara: Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. IEEE Trans. VLSI Syst. 9(1): 42-51 (2001)
	2000
16		Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley: Reconfigurable Array Media Processor (RAMP). FCCM 2000: 287-288
15		Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara: Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. ISLPED 2000: 262-267
14		Uming Ko, Poras T. Balsara: High-performance energy-efficient D-flip-flop circuits. IEEE Trans. VLSI Syst. 8(1): 94-98 (2000)
	1999
13		Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell: Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. VLSI Design 1999: 6-11
12		Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds: High performance low power array multiplier using temporal tiling. IEEE Trans. VLSI Syst. 7(1): 121-124 (1999)
	1998
11		Sharat Prasad, Kamran Kiasaleh, Poras T. Balsara: LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service. INFOCOM 1998: 174-182
10		Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. VLSI Syst. 6(2): 299-308 (1998)
	1996
9		Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara: Leap frog multiplier. ISLPED 1996: 221-223
8		Uming Ko, Anthony M. Hill, Poras T. Balsara: Design techniques for high performance, energy efficient control logic. ISLPED 1996: 97-100
	1995
7		Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multi-level processor cache architectures. ISLPD 1995: 45-49
6		M. Agarwala, Poras T. Balsara: An architecture for a DSP field-programmable gate array. IEEE Trans. VLSI Syst. 3(1): 136-141 (1995)
5		Uming Ko, Poras T. Balsara: Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. VLSI Syst. 3(3): 450-455 (1995)
	1992
4		Poras T. Balsara, Mary Jane Irwin: Intermediate-level vision tasks on a memory array architecture. Mach. Vis. Appl. 6(1): 50-65 (1992)
	1991
3		Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin: Digit Serial Multipliers. J. Parallel Distrib. Comput. 11(2): 156-162 (1991)
2		Poras T. Balsara, Mary Jane Irwin: Image processing on a memory array architecture. VLSI Signal Processing 2(4): 313-324 (1991)
	1987
1		Poras T. Balsara, Robert Michael Owens: Systolic & semi-systolic digit serial multipliers. IEEE Symposium on Computer Arithmetic 1987: 169-173

Coauthor Index

1	M. Agarwala	[6]
2	Mohammad J. Akhbarizadeh	[24] [30]
3	Naofal Al-Dhahir	[42]
4	Dheera Balasubramanian	[37]
5	Bhaskar Banerjee	[51]
6	Imran Bashir	[51]
7	Rajarshee P. Bharadwaj	[31] [32] [33]
8	Dinesh Bhatia	[29] [31] [32] [33] [37]
9	Shilpa Bhoj	[37]
10	Tom Bonifield	[21] [22]
11	Frank Cano	[21]
12	Cyrus D. Cantrell	[13] [18] [20] [21] [27]
13	Raghunath Cherukuri	[38]
14	Mukesh Chugh	[29]
15	Imtinan Elahi	[44]
16	Oren Eliezer (Oren E. Eliezer)	[35] [40] [41] [45] [46] [51]
17	Mitch Entezari	[46]
18	Chan Fernando	[23]
19	Jose Flores	[16]
20	Patrick Friel	[16]
21	Roger Griesmer	[22]
22	Pawan Hegde (Pawankumar Hegde)	[49] [50]
23	Anthony M. Hill	[8]
24	Chih-Ming Hung	[25]
25	William R. Hunter	[27]
26	Mary Jane Irwin	[2] [3] [4]
27	Tom Jung	[25]
28	Kamran Kiasaleh	[11]
29	Uming Ko	[5] [7] [8] [10] [14]
30	Jinseok Koh	[25]
31	Rajan Konar	[31] [32] [33]
32	Mak Kulkarni	[21]
33	Mangesh K. Kunchamwar	[50]
34	Dirk Leipold	[25]
35	Carl Lemonds	[9] [12]
36	Kenneth Maggio	[25]
37	Shivaling S. Mahant-Shetti	[9] [12]
38	Sujan K. Manohar	[53] [54]
39	Jaimin Mehta	[40] [41] [46]
40	Khurram Muhammad	[15] [17] [19] [44]
41	N. S. Nagaraj	[20] [21] [22] [27]
42	Tanvi Nagda	[37]
43	Ashwini K. Nanda	[7] [10]
44	Usha Narasimha	[21]
45	Vishal Nawathe	[49]
46	Mehrdad Nourani	[24] [30] [36]
47	Nagaraj Ns	[13] [18]
48	Vojin G. Oklobdzija	[49]
49	Robert Michael Owens	[1] [3]
50	Viral K. Parikh	[40] [41] [45]
51	Durga P. Prasad	[50]
52	Sharat Prasad	[11]
53	Sushma Honnavara Prasad	[39]
54	V. Ramakrishnan	[34]
55	Kamlesh Rath	[16]
56	Sameh Rezeq	[46]
57	Rama Sangireddy	[50]
58	Abha Singh	[21] [22]
59	Chitranjan K. Singh	[39] [42] [48]
60	Sanjay Pratap Singh	[37]
61	Vinod K. Somasundar	[54]
62	Venkata K. Kidambi Srinivasan	[48]
63	Robert B. Staszewski (Robert Bogdan Staszewski)	[15] [17] [19] [23] [25] [28] [43] [46] [47] [51]
64	Roman Staszewski	[25] [28] [49]
65	Ioannis L. Syllaios	[35] [43] [47] [52]
66	Sirisha Tangirala	[16]
67	Ramakrishnan Venkatasubramanian	[53] [54]
68	Deepak S. Vijayasarathi	[24] [30] [36]
69	Ramaprasath Vilangudipitchai	[26]
70	John P. Wadley	[16]
71	John L. Wallberg	[25]
72	Lei Wang	[49]
73	Vasile Zoicas	[46]

Colors in the list of coauthors

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