Sandeep Baldawa

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2009

2 Hui Wang, Rama Sangireddy, Sandeep Baldawa: Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. IEEE Trans. Parallel Distrib. Syst. 20(3): 389-403 (2009)

2008

1 Hui Wang, Sandeep Baldawa, Rama Sangireddy: Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. VLSI Design 2008: 279-285

	2009
2		Hui Wang, Rama Sangireddy, Sandeep Baldawa: Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. IEEE Trans. Parallel Distrib. Syst. 20(3): 389-403 (2009)
	2008
1		Hui Wang, Sandeep Baldawa, Rama Sangireddy: Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. VLSI Design 2008: 279-285

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