 | 1998 |
|---|
| 10 |       | Alessandro Balboni,
Claudio Costi,
Massimo Pellencin,
Andrea Quadrini,
Donatella Sciuto:
Clock skew reduction in ASIC logic design: a methodology for clock tree management.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 344-356 (1998) |
| 1996 |
|---|
| 9 | | Alessandro Balboni,
William Fornaciari,
Donatella Sciuto:
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow.
CODES 1996: 62-69 |
| 8 | | Alessandro Balboni,
Loris Valenti:
ASIC Design and FPGA Design: A Unified Design Methodology Applied to Different Technologies.
FPL 1996: 356-360 |
| 7 | | Alessandro Balboni,
William Fornaciari,
M. Vincenzi,
Donatella Sciuto:
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems.
ISSS 1996: 77-82 |
| 6 | | Alessandro Balboni,
William Fornaciari,
Donatella Sciuto:
Co-synthesis and co-simulation of control-dominated embedded systems.
Design Autom. for Emb. Sys. 1(3): 257-289 (1996) |
| 1994 |
|---|
| 5 | | Stefano Antoniazzi,
Alessandro Balboni,
William Fornaciari,
Donatella Sciuto:
A methodology for control-dominated systems codesign.
CODES 1994: 2-9 |
| 4 |  | Alessandro Balboni,
Claudio Costi,
Franco Fummi,
Donatella Sciuto:
From Behavioral Description to Systolic Array Based Architectures.
EDAC-ETC-EUROASIC 1994: 657 |
| 3 | | Donatella Sciuto,
Stefano Antoniazzi,
Alessandro Balboni,
William Fornaciari:
The role of VHDL within the TOSCA hardware/software codesign framework.
EURO-DAC 1994: 612-617 |
| 2 | | Stefano Antoniazzi,
Alessandro Balboni,
William Fornaciari,
Donatella Sciuto:
HW/SW Codesign for Embedded Telecom Systems.
ICCD 1994: 278-281 |
| 1993 |
|---|
| 1 | | Stefano Antoniazzi,
Alessandro Balboni,
William Fornaciari:
X-Nets: A visual formalism for system specification and analysis.
Microprocessing and Microprogramming 38(1-5): 71-78 (1993) |
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