Suresh Balasubramanian

	2012
2		Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain: A 32-core RISC microprocessor with network accelerators, power management and testability features. ISSCC 2012: 58-60
	2006
1		Suresh Balasubramanian, Narayanan Natarajan, Olivier Franza, Chris Gianos: Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains. VLSI Design 2006: 781-785

Coauthor Index

1	Akin Aina	[2]
2	Derek Brasili	[2]
3	David Carlson	[2]
4	Ethan Crain	[2]
5	Bruce Fishbein	[2]
6	Olivier Franza	[1]
7	Chris Gianos	[1]
8	Dan Hartman	[2]
9	Adam Hughes	[2]
10	Anil Jain	[2]
11	Vasu Kandadi	[2]
12	Richard Kessler	[2]
13	Tim Kiszely	[2]
14	Rob Kuhn	[2]
15	Mandar Kulkarni	[2]
16	David Lin	[2]
17	William Lin	[2]
18	Rahul Mehrotra	[2]
19	Scott Meninger	[2]
20	Brian Miller	[2]
21	Narayanan Natarajan	[1]
22	Ilan Pragaspathi	[2]
23	Manan Salvi	[2]
24	Mark Spaeth	[2]
25	Bill Stysiack	[2]
26	Pragati Tiwary	[2]
27	Anand Varadharajan	[2]
28	Joe Vulih	[2]
29	Thucydides Xanthopoulos	[2]
30	Vishnu Yalala	[2]
31	Shi-Huang Yin	[2]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page