Padnamabhan Balasubramanian

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2009

3 Padnamabhan Balasubramanian, D. A. Edwards, C. Brej: Self-timed full adder designs based on hybrid input encoding. DDECS 2009: 56-61

2008

2 Padnamabhan Balasubramanian, D. A. Edwards: A New Design Technique for Weakly Indicating Function Blocks. DDECS 2008: 116-121

1 Padnamabhan Balasubramanian, D. A. Edwards: Efficient Realization of Strongly Indicating Function Blocks. ISVLSI 2008: 429-432

	2009
3		Padnamabhan Balasubramanian, D. A. Edwards, C. Brej: Self-timed full adder designs based on hybrid input encoding. DDECS 2009: 56-61
	2008
2		Padnamabhan Balasubramanian, D. A. Edwards: A New Design Technique for Weakly Indicating Function Blocks. DDECS 2008: 116-121
1		Padnamabhan Balasubramanian, D. A. Edwards: Efficient Realization of Strongly Indicating Function Blocks. ISVLSI 2008: 429-432

Coauthor Index

1 C. Brej [3]

2 D. A. Edwards [1] [2] [3]

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team —

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