M. Balakrishnan

	2012
70		Sonali Chouhan, M. Balakrishnan, Ranjan Bose: System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 586-596 (2012)
	2011
69		Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: Architecture and tools for programmable QCA. FPT 2011: 1-4
68		Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi: Compressing Cache State for Postsilicon Processor Debug. IEEE Trans. Computers 60(4): 484-497 (2011)
67		Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. JETC 7(3): 13 (2011)
	2010
66		Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: A tiled programmable fabric using QCA. FPT 2010: 9-16
65		Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: Clocking-Based Coplanar Wire Crossing Scheme for QCA. VLSI Design 2010: 339-344
64		Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan: Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC 2010: 55-60
	2009
63		Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan: Online cache state dumping for processor debug. DAC 2009: 358-363
62		Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda: A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. DATE 2009: 1018-1023
61		Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan: Cache aware compression for processor debug support. DATE 2009: 208-213
60		Sonali Chouhan, M. Balakrishnan, Ranjan Bose: An experimental validation of system level design space exploration methodology for energy efficient sensor nodes. ISLPED 2009: 355-358
59		Sonali Chouhan, Ranjan Bose, M. Balakrishnan: A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1017-1024 (2009)
58		Sonali Chouhan, Ranjan Bose, M. Balakrishnan: Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes. IEEE Transactions on Wireless Communications 8(10): 5348-5355 (2009)
	2008
57		Sonali Chouhan, M. Balakrishnan, Ranjan Bose: A framework for energy consumption based design space exploration for wireless sensor nodes. ISLPED 2008: 329-334
	2007
56		Ashutosh Pal, M. Balakrishnan: A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. FPL 2007: 517-520
55		M. Balakrishnan, N. Ravisankar, K. Meena, R. Elanchezhian, S. K. Zamir Ahmed: Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands. IICAI 2007: 1533-1541
54		Anup Gangwar, M. Balakrishnan, Anshul Kumar: Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 12(1): (2007)
53		Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. International Journal of Parallel Programming 35(6): 507-527 (2007)
	2006
52		Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan: New approach to architectural synthesis: incorporating QoS constraint. EMSOFT 2006: 301-310
51		Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar: Rapid Resource-Constrained Hardware Performance Estimation. IEEE International Workshop on Rapid System Prototyping 2006: 40-46
50		Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra: Sequential Equivalence Checking. VLSI Design 2006: 18-19
	2005
49		Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735
48		Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee: SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). FPGA 2005: 273
47		M. Balakrishnan, B. S. Panwar: A Specialized Graduate Program in VLSI Design Tools and Technology. MSE 2005: 83-84
46		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: Integrated On-Chip Storage Evaluation in ASIP Synthesis. VLSI Design 2005: 274-279
45		Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan: ADOPT: An Approach to Activity Based Delay Optimization. VLSI Design 2005: 411-416
	2004
44		Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Automatic synthesis of system on chip multiprocessor architectures for process networks. CODES+ISSS 2004: 60-65
43		Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Synthesis of Application Specific Multiprocessor Architectures for Process Networks. VLSI Design 2004: 780-783
42		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: An efficient technique for exploring register file size in ASIP design. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1693-1699 (2004)
	2003
41		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: Exploring Storage Organization in ASIP Synthesis. DSD 2003: 120-127
40		Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar: SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design 2003: 585-
	2002
39		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: An efficient technique for exploring register file size in ASIP synthesis. CASES 2002: 252-261
38		Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel: Scratchpad memory: design alternative for cache on-chip memory in embedded systems. CODES 2002: 73-78
37		M. Balakrishnan, Anshul Kumar, C. P. Joshi: A New Performance Evaluation Approach for System Level Design Space Exploration. ISSS 2002: 180-185
36		M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha: A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7
35		M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke: Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. ISSS 2002: 213-218
34		Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar: Exploring the Number of Register Windows in ASIP Synthesis. VLSI Design 2002: 233-238
33		Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan: A New Divide and Conquer Method for Achieving High Speed Division in Hardware. VLSI Design 2002: 535-540
	2001
32		Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan: Evaluating register file size in ASIP design. CODES 2001: 109-114
31		Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan: Exploring design space of parallel realizations: MPEG-2 decoder case study. CODES 2001: 92-97
30		M. Balakrishnan: A Specialized Graduate Program in VLSI Design: A Success Story. MSE 2001: 85-86
29		Anupam Rastogi, M. Balakrishnan, Anshul Kumar: Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. VLSI Design 2001: 23-28
28		Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: ASIP Design Methodologies : Survey and Issues. VLSI Design 2001: 76-
27		Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan: Analysis of the influence of register file size on energyconsumption, code size, and execution time. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1329-1337 (2001)
	2000
26		Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan: Speeding up power estimation of embedded software. ISLPED 2000: 191-196
25		Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan: Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. VLSI Design 2000: 110-113
24		Arvind Rajawat, M. Balakrishnan, Anshul Kumar: nterface Synthesis: Issues and Approaches. VLSI Design 2000: 92
23		T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik: Processor Evaluation in an Embedded Systems Design Environment. VLSI Design 2000: 98-103
22		M. Balakrishnan, Heman Khanna: Allocation of FIFO structures in RTL data paths. ACM Trans. Design Autom. Electr. Syst. 5(3): 294-310 (2000)
	1999
21		M. Anand, Sanjiv Kapoor, M. Balakrishnan: Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware. FPGA 1999: 249
20		Rashmi Goswami, V. Srinivasan, M. Balakrishnan: MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign. VLSI Design 1999: 128-132
19		Ajoy C. Siddabathuni, M. Balakrishnan: Simulation and Modeling of a Multicast ATM Switch. VLSI Design 1999: 242-
	1998
18		Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar: Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. VLSI Design 1998: 400-405
17		Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee: Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign. VLSI Design 1998: 97-
16		A. R. Naseer, M. Balakrishnan, Anshul Kumar: Direct mapping of RTL structures onto LUT-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 624-631 (1998)
	1997
15		M. Balakrishnan, R. Cohen: Global Optimization of Multiplexed Video Encoders. ICIP (1) 1997: 377-
14		Heman Khanna, M. Balakrishnan: Allocation of FIFO Structures in RTL Data Paths. VLSI Design 1997: 130-133
13		A. R. Naseer, M. Balakrishnan, Anshul Kumar: Optimal Clock Period for Synthesized Data Paths. VLSI Design 1997: 134-139
12		Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar: A Novel Reconfigurable Co-Processor Architecture. VLSI Design 1997: 370-375
	1995
11		A. R. Naseer, M. Balakrishnan, Anshul Kumar: Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. FPL 1995: 139-148
10		M. Balakrishnan: Buffer constraints in a variable-rate packetized video system. ICIP 1995: 29-32
9		Alok Kumar, Anshul Kumar, M. Balakrishnan: Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. VLSI Design 1995: 75-80
	1994
8		A. R. Naseer, M. Balakrishnan, Anshul Kumar: An Efficient Technique for Mapping RTL Structures onto FPGAs. FPL 1994: 99-110
7		Atul Varshneya, B. B. Madan, M. Balakrishnan: Concurrent Search and Insertion in K-Dimensional Height Balanced Trees. IPPS 1994: 883-887
6		A. R. Naseer, M. Balakrishnan, Anshul Kumar: FAST: FPGA Targeted RTL Structure Synthesis Technique. VLSI Design 1994: 21-24
	1993
5		C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer: High Level Design Experiences with IDEAS. VLSI Design 1993: 110
4		M. V. Rao, M. Balakrishnan, Anshul Kumar: DESSERT: Design Space Exploration of RT Level Components. VLSI Design 1993: 299-304
	1989
3		M. Balakrishnan, Peter Marwedel: Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. DAC 1989: 68-74
	1988
2		M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia: Allocation of multiport memories in data path synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 536-540 (1988)
1		M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders: A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27(1): 1-7 (1988)

Coauthor Index

1	Mayank Agarwal	[48]
2	Gaurav Aggarwal	[12]
3	Kamal Aggarwal	[12]
4	S. K. Zamir Ahmed	[55]
5	C. S. Ajay	[5]
6	M. Anand	[21]
7	Gaurav Arora	[45]
8	Rajeshwari Banakar	[35] [38]
9	Subhashis Banerjee	[17] [48]
10	Dilip K. Banerji (D. K. Banerji)	[1] [2]
11	Vishal P. Bhatt	[34]
12	Ranjan Bose	[57] [58] [59] [60] [70]
13	Amit Chhabra	[40]
14	Sonali Chouhan	[57] [58] [59] [60] [70]
15	R. Cohen	[15]
16	Rajeswari Devadoss	[65] [66] [67] [69]
17	Harsh Dhand	[52]
18	Basant Kumar Dwivedi	[31] [40] [43] [44] [51] [52]
19	R. Elanchezhian	[55]
20	Masahiro Fujita	[50]
21	Anup Gangwar	[36] [40] [48] [49] [53] [54]
22	Rashmi Goswami	[20]
23	Nils Grunwald	[35]
24	Shashank Gupta	[17]
25	T. Vinod Kumar Gupta	[23]
26	D. Harikrishna	[5]
27	Jan Hoogerbrugge	[31]
28	Paolo Ienne	[36]
29	Manoj Kumar Jain	[27] [28] [32] [39] [41] [42] [46]
30	Sitanshu Jain	[18]
31	C. P. Joshi	[37]
32	Sanjiv Kapoor	[21] [25]
33	M. Karunakaran	[5]
34	Arun Kejariwal	[51]
35	Heman Khanna	[14] [22]
36	Rohini Krishnan	[33]
37	Alok Kumar	[9]
38	Anshul Kumar	[4] [5] [6] [8] [9] [11] [13] [16] [18] [24] [28] [29] [33] [34] [36] [37] [39] [40] [41] [42] [43] [44] [46] [49] [51] [53] [54]
39	Mohit Kumar	[25]
40	Shashi Kumar	[5] [12] [18] [25]
41	Bo-Sik Lee	[38]
42	James G. Linders	[1] [2]
43	Sandeep K. Lodha	[17]
44	B. B. Madan	[7]
45	Jayanti C. Majithia	[2]
46	Arun K. Majumdar	[1] [2]
47	Sharad Malik	[23]
48	Peter Marwedel	[3] [27] [32] [35] [38]
49	Ankit Mathur	[48]
50	Anmol Mathur	[50]
51	K. Meena	[55]
52	Bhuvan Middha	[36]
53	Raj S. Mitra	[50]
54	Soumyadeb Mitra	[48]
55	Murali Mohan	[33]
56	V. Mudgil	[5]
57	D. Nagchoudhuri	[45]
58	A. R. Naseer	[5] [6] [8] [11] [13] [16]
59	Ashutosh Pal	[56]
60	Preeti Ranjan Panda	[49] [53] [61] [62] [63] [64] [68]
61	B. S. Panwar	[47]
62	Kolin Paul	[65] [66] [67] [69]
63	Arvind Rajawat	[24]
64	M. V. Rao	[4]
65	Anupam Rastogi	[29]
66	N. Ravisankar	[55]
67	Aryabartta Sahu	[62]
68	Akshaye Sama	[26]
69	Abhishek Sharma	[45]
70	Purvesh Sharma	[23]
71	Aviral Shrivastava	[25]
72	Ajoy C. Siddabathuni	[19]
73	Amarjeet Singh	[40]
74	V. Srinivasan	[20]
75	Stefan Steinke	[27] [32] [35] [38]
76	Paul Stravers	[31]
77	S. Sutarwala	[1]
78	Nitin Thaper	[12]
79	J. F. M. Theeuwen	[26]
80	Atul Varshneya	[7]
81	Anant Vishnoi	[61] [63] [64] [68]
82	Lars Wehmeyer	[27] [32] [35]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page