Kedarnath J. Balakrishnan

	2009
21		Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield: Test access mechanism for multiple identical cores. ITC 2009: 1-10
20		Kedarnath J. Balakrishnan, Grady Giles, James Wingfield: Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor. IEEE Design & Test of Computers 26(1): 52-59 (2009)
	2008
19		Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield: Test Access Mechanism for Multiple Identical Cores. ITC 2008: 1-10
18		Seongmoon Wang, Kedarnath J. Balakrishnan, Wenlong Wei: X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors. IEEE Trans. Computers 57(7): 978-989 (2008)
	2007
17		Quming Zhou, Kedarnath J. Balakrishnan: Test cost reduction for SoC using a combined approach to test data compression and test scheduling. DATE 2007: 39-44
16		Kedarnath J. Balakrishnan: Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding. VLSI Design 2007: 345-350
15		Kedarnath J. Balakrishnan, Lei Fang: RTL Test Point Insertion to Reduce Delay Test Volume. VTS 2007: 325-332
14		Kedarnath J. Balakrishnan, Nur A. Touba: Relationship Between Entropy and Test Data Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 386-395 (2007)
	2006
13		Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar: Efficient unknown blocking using LFSR reseeding. DATE 2006: 1051-1052
12		Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar: PIDISC: Pattern Independent Design Independent Seed Compression Technique. VLSI Design 2006: 811-817
11		Kedarnath J. Balakrishnan, Nur A. Touba: Improving Linear Test Data Compression. IEEE Trans. VLSI Syst. 14(11): 1227-1237 (2006)
	2005
10		Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil: Compressing Functional Tests for Microprocessors. Asian Test Symposium 2005: 428-433
9		Kedarnath J. Balakrishnan: Emerging Techniques for Test Data Compression. Asian Test Symposium 2005: 462
8		Kedarnath J. Balakrishnan, Nur A. Touba: Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. DATE 2005: 1130-1135
7		Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar: XWRC: externally-loaded weighted random pattern testing for input test data compression. ITC 2005: 10
	2004
6		Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan: Re-configurable embedded core test protocol. ASP-DAC 2004: 234-237
5		Kedarnath J. Balakrishnan, Nur A. Touba: Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. ITC 2004: 936-944
4		Kedarnath J. Balakrishnan, Nur A. Touba: Matrix-based software test data decompression for systems-on-a-chip. Journal of Systems Architecture 50(5): 247-256 (2004)
	2003
3		Kedarnath J. Balakrishnan, Nur A. Touba: Scan-Based BIST Diagnosis Using an Embedded Processor. DFT 2003: 209-216
2		Kedarnath J. Balakrishnan, Nur A. Touba: Deterministic Test Vector Decompression in Software Using Linear Operations. VTS 2003: 225-231
	2002
1		Kedarnath J. Balakrishnan, Nur A. Touba: Matrix-Based Test Vector Decompression Using an Embedded Processor. DFT 2002: 159-165

Coauthor Index

1	Srimat T. Chakradhar	[6] [7] [12] [13]
2	Lei Fang	[15]
3	Grady Giles	[19] [20] [21]
4	Srinivas Patil	[10]
5	Anuja Sehgal	[19] [21]
6	Nur A. Touba	[1] [2] [3] [4] [5] [8] [10] [11] [14]
7	Jing Wang	[19] [21]
8	Seongmoon Wang	[6] [7] [12] [13] [18]
9	Wenlong Wei	[18]
10	James Wingfield	[19] [20] [21]
11	Quming Zhou	[17]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page