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Rajnish Bajpai Coauthor index pubzone.org

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DBLP keys2007
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHimanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Partial Reversible Gates(PRG) for Reversible BCD Arithmetic. CDES 2007: 90-94
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHimanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. PDPTA 2007: 449-452
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHimanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs CoRR abs/0711.2671: (2007)
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHimanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma: Partial Reversible Gates(PRG) for Reversible BCD Arithmetic CoRR abs/0711.2674: (2007)
2006
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHimanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia: Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations. CDES 2006: 130-134

Coauthor Index

1Hamid R. Arabnia [1] [2] [3] [4] [5]
2A. Rameshwar [1]
3Kamal K. Sharma [2] [3] [4] [5]
4Himanshu Thapliyal [1] [2] [3] [4] [5]

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