Dong Hyun Baik

	2007
9		Kim T. Le, Dong Hyun Baik, Kewal K. Saluja: Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. VLSI Design 2007: 769-774
	2006
8		Dong Hyun Baik, Kewal K. Saluja: Test Cost Reduction Using Partitioned Grid Random Access Scan. VLSI Design 2006: 169-174
	2005
7		Dong Hyun Baik, Kewal K. Saluja: State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. Asian Test Symposium 2005: 272-277
6		Dong Hyun Baik, Kewal K. Saluja: Progressive random access scan: a simultaneous solution to test power, test data volume and test time. ITC 2005: 10
5		Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426
4		Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Design & Test of Computers 22(3): 214-222 (2005)
	2004
3		Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD 2004: 611-618
2		Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara: Random Access Scan: A solution to test power, test data volume and test time. VLSI Design 2004: 883-888
	2003
1		Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja: Exclusive Test and its Applications to Fault Diagnosis. VLSI Design 2003: 143-148

Coauthor Index

1	Vishwani D. Agrawal	[1]
2	Charlie Chung-Ping Chen (Chung-Ping Chen)	[3] [4] [5]
3	Seiji Kajihara	[2]
4	Yong Chang Kim	[1]
5	Kim T. Le	[9]
6	Kewal K. Saluja	[1] [2] [3] [4] [5] [6] [7] [8] [9]
7	Jeng-Liang Tsai	[3] [4] [5]

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