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Sudarshan Bahukudumbi Coauthor index pubzone.org

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DBLP keys2009
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishnendu Chakrabarty: Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In. IEEE Trans. VLSI Syst. 17(12): 1730-1741 (2009)
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar: Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs. IEEE Trans. VLSI Syst. 17(4): 587-592 (2009)
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishnendu Chakrabarty: Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 111-120 (2009)
2008
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz: Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. DATE 2008: 1103-1106
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishnendu Chakrabarty: Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. VTS 2008: 193-198
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty: Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
2007
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar: AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC 2007: 823-828
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishnendu Chakrabarty: Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. VLSI Design 2007: 459-464
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishnendu Chakrabarty: Wafer-Level Modular Testing of Core-Based SoCs. IEEE Trans. VLSI Syst. 15(10): 1144-1154 (2007)
2006
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishnendu Chakrabarty: Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs. ITC 2006: 1-10
2005
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudarshan Bahukudumbi, Krishna Bharath: A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. VLSI Design 2005: 804-807

Coauthor Index

1Krishna Bharath [1]
2Krishnendu Chakrabarty [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
3Vikram Iyengar [5] [10]
4Richard Kacprowicz [8]
5Sule Ozev [5] [10]
6Anuja Sehgal [6]

Colors in the list of coauthors

Last update Sat May 26 04:23:17 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page