 | 2012 |
| 12 |  | W.-H. Hu,
C.-Y. Chen,
Jun Ho Bahn,
Nader Bagherzadeh:
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform.
IET Computers & Digital Techniques 6(2): 86-94 (2012) |
| 2010 |
| 11 |  | Yoon Seok Yang,
Jun Ho Bahn,
Seung Eun Lee,
Jungsook Yang,
Nader Bagherzadeh:
Parallel processing for block ciphers on a fault tolerant networked processor array.
IJHPSA 2(3/4): 156-167 (2010) |
| 2009 |
| 10 |  | Yoon Seok Yang,
Jun Ho Bahn,
Seung Eun Lee,
Nader Bagherzadeh:
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip.
ITNG 2009: 849-854 |
| 9 |  | Wen-Hsiang Hu,
Jun Ho Bahn,
Nader Bagherzadeh:
Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform.
SBAC-PAD 2009: 35-40 |
| 8 |  | Jun Ho Bahn,
Jungsook Yang,
Wen-Hsiang Hu,
Nader Bagherzadeh:
Parallel FFT Algorithms on Network-on-Chips.
Journal of Circuits, Systems, and Computers 18(2): 255-269 (2009) |
| 2008 |
| 7 |  | Seung Eun Lee,
Jun Ho Bahn,
Yoon Seok Yang,
Nader Bagherzadeh:
A Generic Network Interface Architecture for a Networked Processor Array (NePA).
ARCS 2008: 247-260 |
| 6 |  | Jun Ho Bahn,
Jungsook Yang,
Nader Bagherzadeh:
Parallel FFT Algorithms on Network-on-Chips.
ITNG 2008: 1087-1093 |
| 5 |  | Jun Ho Bahn,
Nader Bagherzadeh:
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router.
IET Computers & Digital Techniques 2(1): 63-73 (2008) |
| 4 |  | Jun Ho Bahn,
Seung Eun Lee,
Yoon Seok Yang,
Jungsook Yang,
Nader Bagherzadeh:
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture.
Parallel Processing Letters 18(2): 239-255 (2008) |
| 2007 |
| 3 |  | Jun Ho Bahn,
Seung Eun Lee,
Nader Bagherzadeh:
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture.
ITNG 2007: 1033-1038 |
| 2 |  | Seung Eun Lee,
Jun Ho Bahn,
Nader Bagherzadeh:
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).
SBAC-PAD 2007: 211-218 |
| 1 |  | Jun Ho Bahn,
Seung Eun Lee,
Nader Bagherzadeh:
Design of a router for network-on-chip.
IJHPSA 1(2): 98-105 (2007) |