R. Iris Bahar

	2012
73		Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy: A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. ACM Great Lakes Symposium on VLSI 2012: 39-44
	2011
72		Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy: SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. CODES+ISSS 2011: 39-48
71		Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar: Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. European Test Symposium 2011: 211
70		Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal: Enhancing online error detection through area-efficient multi-site implications. VTS 2011: 241-246
69		Desta Tadesse, R. Iris Bahar, Joel Grodstein: Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. J. Electronic Testing 27(2): 123-136 (2011)
	2010
68		R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010 ACM 2010
67		Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI 2010: 131-134
66		Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ACM Great Lakes Symposium on VLSI 2010: 281-286
65		Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. HiPEAC 2010: 50-65
64		Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. IEEE Trans. VLSI Syst. 18(11): 1608-1620 (2010)
63		Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 788-801 (2010)
62		Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. J. Parallel Distrib. Comput. 70(10): 1042-1052 (2010)
61		Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Dual-Vt assignment policies in ITD-aware synthesis. Microelectronics Journal 41(9): 547-553 (2010)
	2009
60		Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 ACM 2009
59		Cesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino: Energy-optimal synchronization primitives for single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2009: 141-144
58		Roto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI 2009: 251-256
57		Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: Detecting errors using multi-cycle invariance information. DATE 2009: 791-796
56		Roto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA 2009: 286
55		Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal: Compacting test vector sets via strategic use of implications. ICCAD 2009: 83-88
54		Sherief Reda, Aung Si, R. Iris Bahar: Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED 2009: 283-286
53		Desta Tadesse, Joel Grodstein, R. Iris Bahar: AutoRex: An automated post-silicon clock tuning tool. ITC 2009: 1-10
52		R. Iris Bahar: Introduction to special section: Best of NANOARCH 2008. JETC 5(2): (2009)
	2008
51		Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy efficient synchronization techniques for embedded architectures. ACM Great Lakes Symposium on VLSI 2008: 435-440
50		Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar: Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10
49		Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220
48		Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar: Using Implications for Online Error Detection. ITC 2008: 1-10
47		Desta Tadesse, R. Iris Bahar, Joel Grodstein: Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. VTS 2008: 339-344
46		R. Iris Bahar, Krishnendu Chakrabarty: Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
45		Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino: Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electronics 4(3): 374-384 (2008)
44		R. Iris Bahar, Krishnendu Chakrabarty: Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. JETC 4(2): (2008)
43		Cesare Ferri, Sherief Reda, R. Iris Bahar: Parametric yield management for 3D ICs: Models and strategies for improvement. JETC 4(4): (2008)
	2007
42		Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein: Accurate timing analysis using SAT and pattern-dependent delay models. DATE 2007: 1018-1023
41		Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581
40		Cesare Ferri, Sherief Reda, R. Iris Bahar: Strategies for improving the parametric yield and profits of 3D ICs. ICCAD 2007: 220-226
39		R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram: Architectures for Silicon Nanoelectronics and Beyond. IEEE Computer 40(1): 25-33 (2007)
38		Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electronic Testing 23(2-3): 255-266 (2007)
37		Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy: A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Computer Architecture News 35(1): 47-54 (2007)
	2006
36		Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152
35		Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss: A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. DAC 2006: 705-708
34		Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793
33		R. Iris Bahar: Trends and Future Directions in Nano Structure Based Computing and Fabrication. ICCD 2006
32		Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy implications of multiprocessor synchronization. SPAA 2006: 329
31		Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006)
30		Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein: Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1815-1830 (2006)
	2005
29		Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490
28		Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy reduction in multiprocessor systems using transactional memory. ISLPED 2005: 331-334
27		R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi: Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. IEEE Design & Test of Computers 22(4): 295-297 (2005)
26		R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein: Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 502-515 (2005)
	2004
25		Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI 2004: 407-412
24		Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss: Fetch Halting on Critical Load Misses. ICCD 2004: 244-249
23		Yu Bai, R. Iris Bahar: Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. ICCD 2004: 54-57
22		Tali Moreshet, R. Iris Bahar: Effects of speculation on performance and issue queue design. IEEE Trans. VLSI Syst. 12(10): 1123-1126 (2004)
21		Yu Bai, R. Iris Bahar: A low-power in-order/out-of-order issue queue. TACO 1(2): 152-179 (2004)
	2003
20		Tali Moreshet, R. Iris Bahar: Power-aware issue queue design for speculative instructions. DAC 2003: 634-637
19		R. Iris Bahar, Joseph L. Mundy, Jie Chen: A Probabilistic-Based Design Methodology for Nanoscale Computation. ICCAD 2003: 480-486
18		Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein: Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. ICCD 2003: 70-75
17		Yu Bai, R. Iris Bahar: A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. ISVLSI 2003: 139-148
16		Eric Chi, A. Michael Salem, R. Iris Bahar, Richard S. Weiss: Combining Software and Hardware Monitoring for Improved Power and Performance Tuning. Interaction between Compilers and Computer Architectures 2003: 57-64
	2002
15		Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS 2002: 203-208
	2001
14		R. Iris Bahar, Srilatha Manne: Power and energy reduction via pipeline balancing. ISCA 2001: 218-229
	2000
13		Roberto Maro, Yu Bai, R. Iris Bahar: Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. PACS 2000: 97-111
12		R. Iris Bahar, Ernest T. Lampe, Enrico Macii: Power optimization of technology-dependent circuits based on symbolic computation of logic implications. ACM Trans. Design Autom. Electr. Syst. 5(3): 267-293 (2000)
	1999
11		Brian R. Fisk, R. Iris Bahar: The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. ICCD 1999: 538-545
	1998
10		R. Iris Bahar, Gianluca Albera, Srilatha Manne: Power and performance tradeoffs using various caching strategies. ISLPED 1998: 64-69
	1997
9		R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic Decision Diagrams and Their Applications. Formal Methods in System Design 10(2/3): 171-206 (1997)
8		R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1101-1115 (1997)
	1996
7		R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi: Symbolic computation of logic implications for technology-dependent low-power synthesis. ISLPED 1996: 163-168
	1995
6		Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino: Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28
5		R. Iris Bahar, Fabio Somenzi: Boolean techniques for low power driven re-synthesis. ICCAD 1995: 428-432
4		Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi: CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD 1995: 111-116
	1994
3		R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Timing Analysis of Combinational Circuits using ADD's. EDAC-ETC-EUROASIC 1994: 625-629
2		R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: A symbolic method to reduce power consumption of circuits containing false paths. ICCAD 1994: 368-371
	1993
1		R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic decision diagrams and their applications. ICCAD 1993: 188-191

Coauthor Index

1	Gianluca Albera	[10]
2	Nuno Alves	[48] [55] [57] [63] [67] [70] [71]
3	David Atienza (David Atienza Alonso)	[68]
4	Yu Bai	[13] [17] [21] [23]
5	Luca Benini	[37] [72]
6	Sanjukta Bhanja	[60]
7	S. Bohidar	[18]
8	Erik Brunvand	[68]
9	Alison Buben	[63]
10	M. Burns	[7]
11	Andrea Calimera	[45] [49] [50] [61] [64]
12	Krishnendu Chakrabarty	[44] [46]
13	Jie Chen	[19]
14	Eric Chi	[16]
15	Hyunwoo Cho	[3] [8]
16	Fabio Cremona	[73]
17	Marco Donato	[73]
18	Karthik Duraisami	[45]
19	Jennifer Dworak	[35] [48] [55] [57] [63] [67] [70] [71]
20	Peter Feldmann	[4]
21	Cesare Ferri	[37] [40] [43] [51] [59] [62] [65] [72]
22	Brian R. Fisk	[11]
23	Erica A. Frohm	[1] [9]
24	Charles M. Gaona	[1] [9]
25	Joel Grodstein	[15] [18] [25] [26] [30] [42] [47] [53] [69]
26	Gary D. Hachtel	[1] [2] [3] [4] [6] [7] [8] [9]
27	Dan W. Hammerstrom	[39]
28	Justin E. Harlow III	[39]
29	Maurice Herlihy	[28] [32] [37] [51] [62] [65] [72]
30	N. Imbriglia	[71]
31	Pooya Jannaty	[66]
32	Warren Jin	[73]
33	William H. Joyner Jr.	[39]
34	Ernest T. Lampe	[12]
35	Clifford Lau	[39]
36	Roto Le	[56] [58]
37	E. Lenge	[42]
38	Michael Leuchtenburg	[24]
39	Benjamin Lipton	[72]
40	Mirko Loghi	[59]
41	Fabrizio Lombardi	[27] [60] [68]
42	Alberto Macii	[45]
43	Enrico Macii	[1] [2] [3] [6] [7] [8] [9] [12] [45] [49] [50] [61] [64]
44	Srilatha Manne	[4] [6] [10] [14]
45	Diana Marculescu	[39]
46	Roberto Maro	[13]
47	Andrea Marongiu	[72]
48	Yehia Massoud	[60]
49	Nikil Mehta	[24]
50	Tali Moreshet	[20] [22] [28] [32] [37] [51] [62] [65] [72]
51	Joseph L. Mundy	[19] [29] [31] [34] [36] [38] [41] [66] [73]
52	Kundan Nepal	[25] [26] [29] [30] [31] [34] [36] [38] [41] [48] [55] [57] [63] [67] [70] [71]
53	Alex Orailoglu	[39]
54	Abelardo Pardo	[1] [4] [6] [9]
55	William R. Patterson	[29] [31] [34] [36] [38] [41] [66] [73]
56	Massoud Pedram	[39]
57	Massimo Poncino	[6] [45] [49] [50] [59] [61] [64]
58	Sherief Reda	[40] [43] [54] [56] [58]
59	Florian C. Sabou	[66]
60	A. Michael Salem	[16]
61	Ashoka Visweswara Sathanur	[45]
62	D. Sheffield	[42]
63	Y. Shi	[71]
64	Yiwen Shi	[70]
65	H. Shin	[7]
66	Sandeep K. Shukla (Sandeep Kumar Shukla)	[27]
67	Aung Si	[54]
68	Brian Singer	[24]
69	Prassanna Sithambaram	[45]
70	Fabio Somenzi	[1] [2] [3] [4] [5] [6] [7] [8] [9]
71	Hui-Yuan Song	[15] [18] [25] [26] [30]
72	Vladimir Stojanovic	[35]
73	Desta Tadesse	[42] [47] [53] [69]
74	Mehdi Baradaran Tahoori	[27]
75	Amber Viescas	[51]
76	Richard Weiss	[35]
77	Richard S. Weiss	[16] [24]
78	Samantha Wood	[62] [65]
79	Alexander Zaslavsky	[29] [31] [34] [36] [38] [41] [66] [73]

Colors in the list of coauthors

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