 | 2010 |
|---|
| 7 |       | Aritra Hazra,
Srobona Mitra,
Pallab Dasgupta,
Ajit Pal,
Debabrata Bagchi,
Kaustav Guha:
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent.
DAC 2010: 773-776 |
| 2004 |
|---|
| 6 |  | Prithviraj Banerjee,
Malay Haldar,
Anshuman Nayak,
Victor Kim,
Vikram Saxena,
Steven Parkes,
Debabrata Bagchi,
Satrajit Pal,
Nikhil Tripathi,
David Zaretsky,
R. Anderson,
J. R. Uribe:
Overview of a compiler for synthesizing MATLAB programs onto FPGAs.
IEEE Trans. VLSI Syst. 12(3): 312-324 (2004) |
| 2003 |
|---|
| 5 | | Prithviraj Banerjee,
Debabrata Bagchi,
Malay Haldar,
Anshuman Nayak,
Victor Kim,
R. Uribe:
Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design.
FCCM 2003: 263-264 |
| 4 | | Prithviraj Banerjee,
Vikram Saxena,
J. R. Uribe,
Malay Haldar,
Anshuman Nayak,
Victor Kim,
Debabrata Bagchi,
Satrajit Pal,
Nikhil Tripathi,
R. Anderson:
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs.
FPGA 2003: 237 |
| 2002 |
|---|
| 3 | | Alex K. Jones,
Debabrata Bagchi,
Satrajit Pal,
Xiaoyong Tang,
Alok N. Choudhary,
Prithviraj Banerjee:
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.
CASES 2002: 188-197 |
| 2 | | Prithviraj Banerjee,
Malay Haldar,
Anshuman Nayak,
Victor Kim,
Debabrata Bagchi,
Satrajit Pal,
Nikhil Tripathi:
A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs.
IWDC 2002: 246-256 |
| 2001 |
|---|
| 1 | | Debabrata Bagchi,
Dipanwita Roy Chowdhury,
Joy Mukherjee,
Santanu Chattopadhyay:
A Novel Strategy to Test Core Based Designs.
VLSI Design 2001: 122-127 |
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