Sanghyeon Baeg

	2011
14		Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg: Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors. DAC 2011: 700-705
13		Changmin Jung, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong: Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations. ISQED 2011: 390-397
12		Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong: Mitigating the effects of large multiple cell upsets (MCUs) in memories. ACM Trans. Design Autom. Electr. Syst. 16(4): 45 (2011)
	2010
11		Sanghyeon Baeg, Shi-Jie Wen, Richard Wong: Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals. IEEE Trans. on Circuits and Systems 57-I(4): 814-822 (2010)
	2009
10		Sanghyeon Baeg: A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins. IEEE T. Instrumentation and Measurement 58(10): 3450-3456 (2009)
9		Sanghyeon Baeg: Null Detector Circuit Design Scheme for Detecting Defective AC-Coupled Capacitors in Differential Signaling. IEEE T. Instrumentation and Measurement 58(8): 2544-2556 (2009)
	2008
8		Sanghyeon Baeg: Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line. IEEE Trans. on Circuits and Systems 55-I(6): 1485-1494 (2008)
7		Sanghyeon Baeg: Low Power Configuration Strategy of TCAM Lookup Table. IEICE Transactions 91-B(3): 915-917 (2008)
	2007
6		Sanghyeon Baeg: Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2215-2221 (2007)
	2005
5		Sanghyeon Baeg, Sung Soo Chung: Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis. IEEE Trans. VLSI Syst. 13(3): 370-383 (2005)
	2001
4		Sung Soo Chung, Sanghyeon Baeg: AC-JTAG: empowering JTAG beyond testing DC nets. ITC 2001: 30-37
	1999
3		Sanghyeon Baeg, William A. Rogers: A cost-effective design for testability: clock line control and test generation using selective clocking. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 850-861 (1999)
	1994
2		Sanghyeon Baeg, William A. Rogers: A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. ICCD 1994: 354-358
1		Sanghyeon Baeg, William A. Rogers: Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. ITC 1994: 340-349

Coauthor Index

1	Sung Soo Chung	[4] [5]
2	Changmin Jung	[13]
3	Juan Antonio Maestro	[12] [14]
4	Pedro Reviriego	[12] [14]
5	William A. Rogers	[1] [2] [3]
6	Shi-Jie Wen	[11] [12] [13]
7	Richard Wong	[11] [12] [13]

Colors in the list of coauthors

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