Iuliana Bacivarov

	2012
15		Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele: Worst-Case Temperature Guarantees for Real-Time Applications on Multi-core Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2012: 87-96
14		Kai Huang, Wolfgang Haid, Iuliana Bacivarov, Matthias Keller, Lothar Thiele: Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications. ACM Trans. Embedded Comput. Syst. 11(1): 8 (2012)
	2011
13		Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang: Mapping of applications to MPSoCs. CODES+ISSS 2011: 109-118
12		Lothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov: Thermal-aware system analysis and software synthesis for embedded multi-processors. DAC 2011: 268-273
11		Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, Lothar Thiele: Worst-case temperature analysis for real-time systems. DATE 2011: 631-636
10		Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele: Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study. PATMOS 2011: 288-297
	2009
9		Wolfgang Haid, Lars Schor, Kai Huang, Iuliana Bacivarov, Lothar Thiele: Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs. ESTImedia 2009: 35-44
8		Wolfgang Haid, Matthias Keller, Kai Huang, Iuliana Bacivarov, Lothar Thiele: Generation and calibration of compositional performance analysis models for multi-processor systems. ICSAMOS 2009: 92-99
7		Kai Huang, Iuliana Bacivarov, Jun Liu, Wolfgang Haid: A modular fast simulation framework for stream-oriented MPSoC. SIES 2009: 74-81
	2008
6		Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, Lothar Thiele: Scalably distributed SystemC simulation for embedded applications. SIES 2008: 271-274
	2007
5		Lothar Thiele, Iuliana Bacivarov, Wolfgang Haid, Kai Huang: Mapping Applications to Tiled Multiprocessor Embedded Systems. ACSD 2007: 29-40
	2006
4		Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya: Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE Designers' Forum 2006: 166-171
	2005
3		Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya: Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. ASP-DAC 2005: 969-972
2		Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya: ChronoSym: a new approach for fast and accurate SoC cosimulation. IJES 1(1/2): 103-111 (2005)
	2003
1		Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya: Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. DATE 2003: 10550-10555

Coauthor Index

1	Marius Bonaciu	[3] [4]
2	Aimen Bouchhima	[1] [2] [3]
3	Jian-Jia Chen	[11]
4	Florin Dumitrascu	[4]
5	Soonhoi Ha	[13]
6	Wolfgang Haid	[5] [7] [8] [9] [14]
7	Kai Huang	[5] [6] [7] [8] [9] [14]
8	Lin Huang	[13]
9	Fabian Hugelshofer	[6]
10	Ahmed Amine Jerraya	[1] [2] [3] [4]
11	Matthias Keller	[8] [14]
12	Georgia Kouveli	[13]
13	Chanhee Lee	[13]
14	Jun Liu	[7]
15	Peter Marwedel	[13]
16	Yanick Paviot	[1]
17	Lorenzo Pieralisi	[4]
18	Devendra Rai	[11]
19	Lars Schor	[9] [10] [12] [15]
20	Jürgen Teich	[13]
21	Lothar Thiele	[5] [6] [8] [9] [10] [11] [12] [13] [14] [15]
22	Qiang Xu	[13]
23	Hoeseok Yang	[10] [11] [12] [15]
24	Sungjoo Yoo	[1] [2]
25	Wassim Youssef	[3]

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