 | 2011 |
| 24 |  | Anh Thien Tran,
Bevan M. Baas:
RoShaQ: High-performance on-chip router with shared queues.
ICCD 2011: 232-238 |
| 23 |  | Tinoosh Mohsenin,
Houshmand Shirani-mehr,
Bevan M. Baas:
Low power LDPC decoder with efficient stopping scheme for undecodable blocks.
ISCAS 2011: 1780-1783 |
| 22 |  | Zhibin Xiao,
Bevan M. Baas:
A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System.
IEEE Trans. Circuits Syst. Video Techn. 21(7): 890-902 (2011) |
| 2010 |
| 21 |  | Dean Truong,
Bevan M. Baas:
Circuit modeling for practical many-core architecture design exploration.
DAC 2010: 627-628 |
| 20 |  | Zhiyi Yu,
Bevan M. Baas:
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors.
IEEE Trans. VLSI Syst. 18(5): 750-762 (2010) |
| 19 |  | Anh Thien Tran,
Dean Nguyen Truong,
Bevan M. Baas:
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(6): 897-910 (2010) |
| 18 |  | Tinoosh Mohsenin,
Dean Nguyen Truong,
Bevan M. Baas:
A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders.
IEEE Trans. on Circuits and Systems 57-I(5): 1048-1061 (2010) |
| 17 |  | Tinoosh Mohsenin,
Bevan M. Baas:
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders.
Signal Processing Systems 61(3): 329-345 (2010) |
| 2009 |
| 16 |  | Tinoosh Mohsenin,
Dean Truong,
Bevan M. Baas:
An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes.
ICC 2009: 1-5 |
| 15 |  | Anthony T. Jacobson,
Dean Nguyen Truong,
Bevan M. Baas:
The Design of a Reconfigurable Continuous-flow Mixed-radix FFT Processor.
ISCAS 2009: 1133-1136 |
| 14 |  | Tinoosh Mohsenin,
Dean Nguyen Truong,
Bevan M. Baas:
Multi-Split-Row Threshold Decoding Implementations for LDPC Codes.
ISCAS 2009: 2449-2452 |
| 13 |  | Anh Thien Tran,
Dean Nguyen Truong,
Bevan M. Baas:
A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors.
ISCAS 2009: 996-999 |
| 12 |  | Anh Thien Tran,
Dean Truong,
Bevan M. Baas:
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network.
NOCS 2009: 214-223 |
| 11 |  | Zhiyi Yu,
Bevan M. Baas:
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors.
IEEE Trans. VLSI Syst. 17(1): 66-79 (2009) |
| 2008 |
| 10 |  | Zhibin Xiao,
Bevan M. Baas:
A high-performance parallel CAVLC encoder on a fine-grained many-core system.
ICCD 2008: 248-254 |
| 9 |  | Wayne H. Cheng,
Bevan M. Baas:
Dynamic voltage and frequency scaling circuits with two supply voltages.
ISCAS 2008: 1236-1239 |
| 8 |  | Zhiyi Yu,
Bevan M. Baas:
A low-area interconnect architecture for chip multiprocessors.
ISCAS 2008: 2857-2860 |
| 7 |  | Zhiyi Yu,
Michael J. Meeuwsen,
Ryan W. Apperson,
Omar Sattari,
Michael A. Lai,
Jeremy W. Webb,
Eric W. Work,
Tinoosh Mohsenin,
Bevan M. Baas:
Architecture and Evaluation of an Asynchronous Array of Simple Processors.
Signal Processing Systems 53(3): 243-259 (2008) |
| 2007 |
| 6 |  | Michael J. Meeuwsen,
Zhiyi Yu,
Bevan M. Baas:
A Shared Memory Module for Asynchronous Arrays of Processors.
EURASIP J. Emb. Sys. 2007: (2007) |
| 5 |  | Bevan M. Baas,
Zhiyi Yu,
Michael J. Meeuwsen,
Omar Sattari,
Ryan W. Apperson,
Eric W. Work,
Jeremy W. Webb,
Michael A. Lai,
Tinoosh Mohsenin,
Dean Truong,
Jason Cheung:
AsAP: A Fine-Grained Many-Core Platform for DSP Applications.
IEEE Micro 27(2): 34-45 (2007) |
| 4 |  | Ryan W. Apperson,
Zhiyi Yu,
Michael J. Meeuwsen,
Tinoosh Mohsenin,
Bevan M. Baas:
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.
IEEE Trans. VLSI Syst. 15(10): 1125-1134 (2007) |
| 2006 |
| 3 |  | Zhiyi Yu,
Bevan M. Baas:
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.
ICCD 2006 |
| 2 |  | Tinoosh Mohsenin,
Bevan M. Baas:
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture.
ICCD 2006 |
| 1 |  | Zhiyi Yu,
Bevan M. Baas:
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.
ISVLSI 2006: 378-383 |