 | 2012 |
|---|
| 9 |       | Kashif Latif,
M. Muzaffar Rao,
Athar Mahboob,
Arshad Aziz:
Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms.
ARC 2012: 372-378 |
| 2011 |
|---|
| 8 | | Kashif Latif,
Athar Mahboob,
Arshad Aziz:
High Throughput Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist: BLAKE.
FIT 2011: 189-194 |
| 7 | | Kashif Latif,
Arshad Aziz,
Athar Mahboob:
Optimal utilization of available reconfigurable hardware resources.
Computers & Electrical Engineering 37(6): 1043-1057 (2011) |
| 2010 |
|---|
| 6 | | Dur-e-Shahwar Kundi,
Arshad Aziz,
Nassar Ikram:
Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA.
Inf. Process. Lett. 110(10): 373-377 (2010) |
| 2009 |
|---|
| 5 | | Kashif Latif,
Arshad Aziz,
Athar Mahboob:
Efficient resource utilization of FPGAs.
FIT 2009: 26 |
| 2007 |
|---|
| 4 | | Abdul Samiah,
Arshad Aziz,
Nassar Ikram:
An Efficient Software Implementation of AES-CCM for IEEE 802.11i Wireless St.
COMPSAC (2) 2007: 689-694 |
| 3 |  | Arshad Aziz,
Nassar Ikram:
A Look-Up-Table Implementation of AES.
HPCNCS 2007: 187-191 |
| 2 | | Arshad Aziz,
Nassar Ikram:
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture.
I. J. Network Security 5(2): 224-232 (2007) |
| 1 | | Arshad Aziz,
Nassar Ikram:
Memory Efficient Implementation of AES S-Boxes on FPGA.
Journal of Circuits, Systems, and Computers 16(4): 603-611 (2007) |
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