Mahzad Azarmehr

	2011
4		Mahzad Azarmehr, Roberto Muscedere: A RISC architecture for 2DLNS-based signal processing. IJHPSA 3(2/3): 149-156 (2011)
	2010
3		Mahzad Azarmehr, Majid Ahmadi, Graham A. Jullien: Recursive architectures for 2DLNS multiplication. ISCAS 2010: 3869-3872
2		Mahzad Azarmehr, Rashid Rashidzadeh, Majid Ahmadi: High-speed CMOS track-and-hold with an offset cancellation replica circuit. ISCAS 2010: 4297-4300
	2007
1		Mahzad Azarmehr, Roberto Muscedere: A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions. ASAP 2007: 342-345

Coauthor Index

1	Majid Ahmadi	[2] [3]
2	Graham A. Jullien	[3]
3	Roberto Muscedere	[1] [4]
4	Rashid Rashidzadeh	[2]

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