Nadine Azémard

Nadine Azémard-Crestani

	2012
41		Nadine Azémard, Marc Belleville: Selected Articles from the VARI 2011 Workshop. J. Low Power Electronics 8(1): 82 (2012)
40		Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme: Delay-correlation-aware SSTA based on conditional moments. Microelectronics Journal 43(4): 263-273 (2012)
	2011
39		Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard: Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectronics Journal 42(5): 718-732 (2011)
	2010
38		Nadine Azémard: Selected Peer-Reviewed Articles from the VARI 2010 Workshop. J. Low Power Electronics 6(4): 563 (2010)
37		Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson: On-Chip Process Variability Monitoring Flow. J. Low Power Electronics 6(4): 601-606 (2010)
	2009
36		Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme: Interpreting SSTA Results with Correlation. PATMOS 2009: 16-25
35		Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels: Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS 2009: 247-255
34		Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard: Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS 2009: 266-275
33		V. Migairou, Robin Wilson, Sylvain Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: Timing margin evaluation with a simple statistical timing analysis flow. J. Embedded Computing 3(3): 221-229 (2009)
	2008
32		Bettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard: Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI 2008: 316-321
31		Nadine Azémard, Philippe Maurine, Johan Vounckx: Editorial. Integration 41(1): 1 (2008)
	2007
30		Nadine Azémard, Lars J. Svensson: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings Springer 2007
29		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature and voltage aware timing analysis: application to voltage drops. DATE 2007: 1012-1017
28		V. Migairou, Robin Wilson, Sylvain Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS 2007: 138-147
27		Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol CoRR abs/0710.4760: (2007)
26		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 801-815 (2007)
	2006
25		Johan Vounckx, Nadine Azémard, Philippe Maurine: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings Springer 2006
24		Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Circuit sizing method under delay constraint. ISCAS 2006
23		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Timing analysis in presence of supply voltage and temperature variations. ISPD 2006: 10-16
22		V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine: Statistical Characterization of Library Timing Performance. PATMOS 2006: 468-476
21		B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Logical effort model extension to propagation delay representation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1677-1684 (2006)
20		Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine: A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integration 39(4): 433-456 (2006)
	2005
19		Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645
18		Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Speed Indicators for Circuit Optimization. PATMOS 2005: 618-628
17		B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature Dependency in UDSM Process. PATMOS 2005: 693-703
	2004
16		Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192
15		Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109
14		B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118
13		A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne: Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731
12		B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848
	2003
11		Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460
10		Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69
	2002
9		Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne: Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330
8		Philippe Maurine, Nadine Azémard, Daniel Auvergne: Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257
7		Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1352-1363 (2002)
	2001
6		Nadine Azémard, M. Aline, Daniel Auvergne: Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378
5		Philippe Maurine, Nadine Azémard, Daniel Auvergne: Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312
4		Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335
3		Nadine Azémard, Daniel Auvergne: POPS: A tool for delay/power performance optimization. Journal of Systems Architecture 47(3-4): 375-382 (2001)
	1995
2		S. Turgis, Nadine Azémard, Daniel Auvergne: Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD 1995: 129-134
	1993
1		Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne: Post-layout timing simulation of CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1170-1177 (1993)

Coauthor Index

1	M. Aline	[4] [6]
2	Daniel Auvergne	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [19] [21] [27]
3	Abhishek Bansal	[35]
4	Sebastien Barasinski	[35]
5	Edith Beigné	[34] [39]
6	Marc Belleville	[32] [34] [39] [41]
7	Christian Bernard	[32] [34] [39]
8	Pierre Busson	[35] [37]
9	Denis Deschacht	[1]
10	Gilles R. Ducharme	[36] [40]
11	Vincent Dumettier	[35] [37]
12	Guy Durieu	[35]
13	Sylvain Engels	[20] [21] [22] [28] [33] [35] [37]
14	A. Landrault	[13] [18] [24]
15	B. Lasbouygues	[12] [14] [17] [21] [23] [26] [29]
16	Philippe Maurine	[4] [5] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [31] [32] [33] [34] [35] [36] [37] [39] [40]
17	David Meyer	[35]
18	Xavier Michel	[9] [10] [11] [15] [16] [19] [27]
19	V. Migairou	[22] [28] [33]
20	Nabila Moubdi	[35] [37]
21	Bettina Rebaud	[32] [34] [39]
22	Mustapha Rezzoug	[7]
23	Michel Robert	[1] [13] [32] [34] [39]
24	Lars J. Svensson	[30]
25	Alain Tournier	[35]
26	S. Turgis	[2]
27	Sarah Verhaeren	[35]
28	Alexandre Verle	[10] [11] [15] [16] [18] [19] [24] [27]
29	Johan Vounckx	[25] [31]
30	Robin Wilson	[12] [14] [17] [20] [21] [22] [23] [26] [28] [29] [33] [35] [37]
31	Zeqin Wu	[36] [40]
32	Zequin Wu	[28] [32] [33]

Colors in the list of coauthors

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