Kazushige Ayukawa

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2001

1 Seiji Miura, Kazushige Ayukawa, Takao Watanabe: A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. ISLPED 2001: 358-363

	2001
1		Seiji Miura, Kazushige Ayukawa, Takao Watanabe: A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. ISLPED 2001: 358-363

Coauthor Index

1 Seiji Miura [1]

2 Takao Watanabe [1]

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