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José L. Ayala
List of publications from the DBLP Bibliography Server - FAQ
| 2012 | ||
|---|---|---|
| 30 | José L. Ayala, David Atienza Alonso, Ricardo Reis: VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers Springer 2012 | |
| 2011 | ||
| 29 | David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011 ACM 2011 | |
| 28 | José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings Springer 2011 | |
| 27 | David Cuesta Gómez, José Luis Risco-Martín, José Luis Ayala, José Ignacio Hidalgo: A combination of evolutionary algorithm and mathematical programming for the 3d thermal-aware floorplanning problem. GECCO 2011: 1731-1738 | |
| 26 | Ignacio Arnaldo, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo: Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures. PATMOS 2011: 11-21 | |
| 25 | Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor: Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. VLSI-SoC 2011: 136-141 | |
| 2010 | ||
| 24 | Mohamed M. Sabry, José L. Ayala, David Atienza: Thermal-aware compilation for system-on-chip processing architectures. ACM Great Lakes Symposium on VLSI 2010: 221-226 | |
| 23 | David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii: Thermal-aware floorplanning exploration for 3D multi-core architectures. ACM Great Lakes Symposium on VLSI 2010: 99-102 | |
| 22 | David Cuesta, José L. Ayala, José Ignacio Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii: Adaptive Task Migration Policies for Thermal Control in MPSoCs. ISVLSI 2010: 110-115 | |
| 21 | José Luis Ayala, Cándido Méndez, Marisa López-Vallejo: Thermal analysis and modeling of embedded processors. Computers & Electrical Engineering 36(1): 142-154 (2010) | |
| 20 | Mohamed M. Sabry, José L. Ayala, David Atienza: Thermal-Aware Compilation for Register Window-Based Embedded Processors. Embedded Systems Letters 2(4): 103-106 (2010) | |
| 19 | José L. Ayala, Arvind Sridhar, David Cuesta: Thermal modeling and analysis of 3D multi-processor chips. Integration 43(4): 327-341 (2010) | |
| 2009 | ||
| 18 | José Luis Ayala, David Atienza, Philip Brisk: Thermal-aware data flow analysis. DAC 2009: 613-614 | |
| 17 | Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing, Yusuf Leblebici: Dynamic thermal management in 3D multicore architectures. DATE 2009: 1410-1415 | |
| 16 | José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici: Through Silicon Via-Based Grid for Thermal Control in 3D Chips. NanoNet 2009: 90-98 | |
| 15 | Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing: Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures. VLSI-SoC 2009: 34-55 | |
| 2008 | ||
| 14 | David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijaykrishnan Narayanan: Reliability-aware design for nanometer-scale devices. ASP-DAC 2008: 549-554 | |
| 13 | José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum: A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. IJES 3(4): 285-293 (2008) | |
| 12 | David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo: Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. Integration 41(1): 38-48 (2008) | |
| 11 | Pedro Echeverría Aramendi, José L. Ayala, Marisa López-Vallejo: Power Considerations in Banked CAMs: A Leakage Reduction Approach. VLSI Design 2008: (2008) | |
| 2007 | ||
| 10 | Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo: Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. ISCAS 2007: 121-124 | |
| 9 | Pablo Ituero, José L. Ayala, Marisa López-Vallejo: Leakage-based On-Chip Thermal Sensor for CMOS Technology. ISCAS 2007: 3327-3330 | |
| 8 | José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio: Thermal Characterization and Thermal Management in Processor-Based Systems. Power-aware Computing Systems 2007 | |
| 7 | José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest: Energy-aware compilation and hardware design for VLIW embedded systems. IJES 3(1/2): 73-82 (2007) | |
| 2006 | ||
| 6 | David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo: Compiler-Driven Leakage Energy Reduction in Banked Register Files. PATMOS 2006: 107-116 | |
| 2005 | ||
| 5 | José Luis Ayala, Marisa López-Vallejo: Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. Power-aware Computing Systems 2005 | |
| 4 | José Luis Ayala, Marisa López-Vallejo: Integrating functional and power simulation in embedded systems design. J. Embedded Computing 1(3): 325-340 (2005) | |
| 2003 | ||
| 3 | José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez: Energy Aware Register File Implementation through Instruction Predecode. ASAP 2003: 86-96 | |
| 2 | José L. Ayala, Marisa Luisa López-Vallejo: A Unified Framework for Power-Aware Design of Embedded Systems. PATMOS 2003: 239-248 | |
| 1 | José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo: Power-Aware Compilation for Register File Energy Reduction. International Journal of Parallel Programming 31(6): 451-467 (2003) | |
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