 | 2011 |
| 7 |  | Takao Toi,
Takumi Okamoto,
Toru Awashima,
Kazutoshi Wakabayashi,
Hideharu Amano:
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
IEICE Transactions 94-A(12): 2619-2627 (2011) |
| 2010 |
| 6 |  | Takao Toi,
Takumi Okamoto,
Toru Awashima,
Kazutoshi Wakabayashi,
Hideharu Amano:
Wire congestion aware synthesis for a dynamically reconfigurable processor.
FPT 2010: 300-303 |
| 2006 |
| 5 |  | Takao Toi,
Noritsugu Nakamura,
Yoshinosuke Kato,
Toru Awashima,
Kazutoshi Wakabayashi,
Li Jing:
High-level synthesis challenges and solutions for a dynamically reconfigurable processor.
ICCAD 2006: 702-708 |
| 2005 |
| 4 |  | Katsuaki Deguchi,
Shohei Abe,
Masayasu Suzuki,
Kenichiro Anjo,
Toru Awashima,
Hideharu Amano:
Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor.
ARCS Workshops 2005: 12-18 |
| 3 |  | Yohei Hasegawa,
Shohei Abe,
Hiroki Matsutani,
Hideharu Amano,
Kenichiro Anjo,
Toru Awashima:
An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.
FPT 2005: 163-170 |
| 2004 |
| 2 |  | Noriaki Suzuki,
Shunsuke Kurotaki,
Masayasu Suzuki,
Naoto Kaneko,
Yutaka Yamada,
Katsuaki Deguchi,
Yohei Hasegawa,
Hideharu Amano,
Kenichiro Anjo,
Masato Motomura,
Kazutoshi Wakabayashi,
Takeo Toi,
Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
FCCM 2004: 328-329 |
| 1992 |
| 1 |  | Toru Awashima,
Wataru Yamamoto,
Masao Sato,
Tatsuo Ohtsuki:
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion.
ICCAD 1992: 162-165 |