Panagiotis Athanasopoulos

	2010
6		Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici: Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. VLSI-SoC 2010: 149-154
	2009
5		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286
4		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510
3		Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD 2009: 689-696
2		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2): (2009)
	2008
1		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190

Coauthor Index

1	Philip Brisk	[1] [2] [3] [4] [5]
2	Alessandro Cevrero	[1] [2] [4] [5] [6]
3	Frank K. Gürkaynak	[1] [2]
4	Paolo Ienne	[1] [2] [3] [4] [5]
5	Yusuf Leblebici	[1] [2] [3] [4] [5] [6]
6	Seyed Hosein Attarzadeh Niaki	[2]
7	Chrysostomos Nicopoulos	[2]
8	Hadi Parandeh-Afshar	[1] [2] [4] [5]
9	Maurizio Skerlj	[4] [5]
10	Fengda Sun	[6]
11	Ajay K. Verma	[1] [2]

Last update Sat May 26 04:23:17 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page