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Sameh W. Asaad Coauthor index pubzone.org

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DBLP keys2012
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno: A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. FPGA 2012: 153-162
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLProshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad: Efficient in-system RTL verification and debugging using FPGAs (abstract only). FPGA 2012: 269
2011
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLBharat Sukhwani, Bülent Abali, Bernard Brezzo, Sameh W. Asaad: High-Throughput, Lossless Data Compresion on FPGAs. FCCM 2011: 113-116
2004
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVictor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno: Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI 2004: 448-452
2003
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno: Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter: An innovative low-power high-performance programmable signal processor for digital communications. IBM Journal of Research and Development 47(2-3): 299-326 (2003)
1998
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSameh W. Asaad, Kevin W. Warren: Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. FPL 1998: 278-287
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLStephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin G. Stawiasz: Designing a Testable System on a Chip. VTS 1998: 2-7

Coauthor Index

1Bülent Abali [6]
2S. Basavaiah [1]
3Ralph Bellofatto [7] [8]
4Shay Ben-David [3]
5Marina Biberstein [3]
6Bernard Brezzo [6] [7] [8]
7Arthur A. Bright [1]
8Jeff H. Derby [3]
9Thomas W. Fox [3] [5]
10Amir B. Geva [3]
11Anne-Marie Haen [5]
12Ruud A. Haring [1]
13Bob Havreluk [1]
14Chuck Haymes [7] [8]
15David F. Heidel [1]
16Hillery C. Hunter [3]
17Michael Immediato [1]
18Keith A. Jenkins [1]
19Rajiv V. Joshi [1]
20Krishnan Kailas [3]
21Mohit Kapur [7] [8]
22Steve Klepner [1]
23Stephen V. Kosonocky [1]
24Daniel Littrell [3] [5]
25Jaime H. Moreno [3] [4] [5]
26Dorit Naishlos [3]
27Fredy D. Neeser [3]
28Benjamin D. Parker [1] [8]
29T. V. Rajeevakumar [1]
30Jude A. Rivers [4]
31Thomas Roewer [8]
32Proshanta Saha [7] [8]
33Uzi Shvadron [3]
34Kevin G. Stawiasz [1]
35Bharat Sukhwani [6]
36Todd Takken [8]
37José A. Tierno [8]
38Malcolm S. Ware [3]
39Kevin W. Warren [1] [2]
40John-David Wellman [4]
41Ayal Zaks [3]
42Victor V. Zyuban [3] [5]

Last update Sat May 26 04:23:17 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page