 | 2012 |
| 8 |  | Sameh W. Asaad,
Ralph Bellofatto,
Bernard Brezzo,
Chuck Haymes,
Mohit Kapur,
Benjamin D. Parker,
Thomas Roewer,
Proshanta Saha,
Todd Takken,
José A. Tierno:
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
FPGA 2012: 153-162 |
| 7 |  | Proshanta Saha,
Chuck Haymes,
Ralph Bellofatto,
Bernard Brezzo,
Mohit Kapur,
Sameh W. Asaad:
Efficient in-system RTL verification and debugging using FPGAs (abstract only).
FPGA 2012: 269 |
| 2011 |
| 6 |  | Bharat Sukhwani,
Bülent Abali,
Bernard Brezzo,
Sameh W. Asaad:
High-Throughput, Lossless Data Compresion on FPGAs.
FCCM 2011: 113-116 |
| 2004 |
| 5 |  | Victor V. Zyuban,
Sameh W. Asaad,
Thomas W. Fox,
Anne-Marie Haen,
Daniel Littrell,
Jaime H. Moreno:
Design methodology for semi custom processor cores.
ACM Great Lakes Symposium on VLSI 2004: 448-452 |
| 2003 |
| 4 |  | Jude A. Rivers,
Sameh W. Asaad,
John-David Wellman,
Jaime H. Moreno:
Reducing instruction fetch energy with backwards branch control information and buffering.
ISLPED 2003: 322-325 |
| 3 |  | Jaime H. Moreno,
Victor V. Zyuban,
Uzi Shvadron,
Fredy D. Neeser,
Jeff H. Derby,
Malcolm S. Ware,
Krishnan Kailas,
Ayal Zaks,
Amir B. Geva,
Shay Ben-David,
Sameh W. Asaad,
Thomas W. Fox,
Daniel Littrell,
Marina Biberstein,
Dorit Naishlos,
Hillery C. Hunter:
An innovative low-power high-performance programmable signal processor for digital communications.
IBM Journal of Research and Development 47(2-3): 299-326 (2003) |
| 1998 |
| 2 |  | Sameh W. Asaad,
Kevin W. Warren:
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience.
FPL 1998: 278-287 |
| 1 |  | Stephen V. Kosonocky,
Arthur A. Bright,
Kevin W. Warren,
Ruud A. Haring,
Steve Klepner,
Sameh W. Asaad,
S. Basavaiah,
Bob Havreluk,
David F. Heidel,
Michael Immediato,
Keith A. Jenkins,
Rajiv V. Joshi,
Benjamin D. Parker,
T. V. Rajeevakumar,
Kevin G. Stawiasz:
Designing a Testable System on a Chip.
VTS 1998: 2-7 |