Siamak Arya

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1995

4 Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162

3 Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180

1988

2 Siamak Arya, Blaine Gaither: Parallel algorithm development workbench. SC 1988: 11-17

1985

1 Siamak Arya: An Optimal Instruction-Scheduling Model for a Class of Vector Processors. IEEE Trans. Computers 34(11): 981-995 (1985)

	1995
4		Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162
3		Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180
	1988
2		Siamak Arya, Blaine Gaither: Parallel algorithm development workbench. SC 1988: 11-17
	1985
1		Siamak Arya: An Optimal Instruction-Scheduling Model for a Class of Vector Processors. IEEE Trans. Computers 34(11): 981-995 (1985)

Coauthor Index

1 Sreeram Duvvuru [3] [4]

2 Blaine Gaither [2]

3 Howard Sachs [4]

Colors in the list of coauthors

Last update Sat May 26 04:23:17 2012 CET by the DBLP Team —

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