Ravishankar Arunachalam

	2005
7		Aniket, Ravishankar Arunachalam: Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. VLSI Design 2005: 479-484
	2004
6		Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam: Static Transition Probability Analysis Under Uncertainty. ICCD 2004: 380-386
	2003
5		Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif: Optimal shielding/spacing metrics for low power design. ISVLSI 2003: 167-172
	2001
4		Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi: False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731
	2000
3		Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: TACO: timing analysis with coupling. DAC 2000: 266-269
	1998
2		Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: Determination of worst-case aggressor alignment for delay calculation. ICCAD 1998: 212-219
	1997
1		Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi: CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229

Coauthor Index

1	Emrah Acar	[5]
2	Aniket	[7]
3	R. D. (Shawn) Blanton (Ronald D. Blanton)	[4]
4	Florentin Dartu	[1]
5	Siddharth Garg	[6]
6	Paul D. Gross	[2]
7	Sani R. Nassif	[5]
8	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[1] [2] [3] [4]
9	Karthik Rajagopal	[2] [3]
10	Siddharth Tata	[6]

Colors in the list of coauthors

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