C. Arun

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2011

4 Periyathambi Ezhumalai, A. Chilambuchelvan, C. Arun: Novel NoC Topology Construction for High-Performance Communications. Journal Comp. Netw. and Communic. 2011: (2011)

2010

3 Periyathambi Ezhumalai, S. Manojkumar, C. Arun, P. Sakthivel, D. Sridharan: High Performance Hybrid Two Layer Router Architecture for FPGAs Using Network On Chip CoRR abs/1002.2420: (2010)

2009

2 C. Arun, V. Rajamani: A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering. IJCNS 2(6): 575-582 (2009)

2007

1 C. Arun, V. Rajamani: Minimized Memory Architecture for Low Latency Viterbi Decoder Using Zig-Zag Algorithm. I. J. Wireless & Optical Communications 4(3): 313-323 (2007)

	2011
4		Periyathambi Ezhumalai, A. Chilambuchelvan, C. Arun: Novel NoC Topology Construction for High-Performance Communications. Journal Comp. Netw. and Communic. 2011: (2011)
	2010
3		Periyathambi Ezhumalai, S. Manojkumar, C. Arun, P. Sakthivel, D. Sridharan: High Performance Hybrid Two Layer Router Architecture for FPGAs Using Network On Chip CoRR abs/1002.2420: (2010)
	2009
2		C. Arun, V. Rajamani: A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering. IJCNS 2(6): 575-582 (2009)
	2007
1		C. Arun, V. Rajamani: Minimized Memory Architecture for Low Latency Viterbi Decoder Using Zig-Zag Algorithm. I. J. Wireless & Optical Communications 4(3): 313-323 (2007)

Coauthor Index

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