Adrià Armejach

	2012
4		Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero: Circuit design of a dual-versioning L1 data cache. Integration 45(3): 237-245 (2012)
	2011
3		Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero: Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330
2		Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero: Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT 2011: 361-371
	2009
1		Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero: EazyHTM: eager-lazy hardware transactional memory. MICRO 2009: 145-155

Coauthor Index

1	Adrián Cristal	[1] [2] [3] [4]
2	J. Rubén Titos Gil	[2]
3	Tim Harris	[1]
4	Ibrahim Hur	[2] [3] [4]
5	Chinmay Eishan Kulkarni	[1]
6	Cristian Perfumo	[1]
7	Azam Seyedi	[2] [3] [4]
8	Sasa Tomic	[1]
9	Osman S. Unsal (Osman S. Ünsal)	[1] [2] [3] [4]
10	Mateo Valero	[1] [2] [3] [4]

Last update Sat May 26 04:23:17 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page