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| 2012 | ||
|---|---|---|
| 29 | Kazutami Arimoto, Sam Kavusi, Kenneth Salisbury: What's next in robots? ∼Sensing, processing, networking toward human brain and body. ISSCC 2012: 514 | |
| 2011 | ||
| 28 | Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto: PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. IPDPS Workshops 2011: 871-879 | |
| 27 | Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato: An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC 2011: 266-268 | |
| 26 | Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo: Low Power Platform for Embedded Processor LSIs. IEICE Transactions 94-C(4): 394-400 (2011) | |
| 25 | Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto: A Scalable Massively Parallel Processor for Real-Time Image Processing. J. Solid-State Circuits 46(10): 2363-2373 (2011) | |
| 2010 | ||
| 24 | Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto: A scalable massively parallel processor for real-time image processing. ISSCC 2010: 334-335 | |
| 23 | Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner: Fusion of MEMS and circuits. ISSCC 2010: 526-527 | |
| 22 | Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto: Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC 2010: 519-524 | |
| 2009 | ||
| 21 | Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto: On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Transactions 92-C(3): 356-363 (2009) | |
| 20 | Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto: A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. IEICE Transactions 92-C(4): 453-459 (2009) | |
| 2008 | ||
| 19 | Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Transactions 91-C(9): 1409-1418 (2008) | |
| 2007 | ||
| 18 | Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528 | |
| 17 | Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto: Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43 | |
| 16 | Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto: A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Transactions 90-C(10): 1927-1935 (2007) | |
| 15 | Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu: Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Transactions 90-C(4): 657-665 (2007) | |
| 14 | Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto: A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Transactions 90-C(4): 765-771 (2007) | |
| 13 | Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Transactions 90-D(1): 334-345 (2007) | |
| 12 | Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Transactions 90-D(8): 1312-1315 (2007) | |
| 2006 | ||
| 11 | Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba: An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Transactions 89-C(11): 1519-1525 (2006) | |
| 10 | Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto: A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Transactions 89-C(11): 1612-1619 (2006) | |
| 2005 | ||
| 9 | Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito: CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205 | |
| 8 | Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara: A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Transactions 88-C(10): 2020-2027 (2005) | |
| 7 | Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara: Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Transactions 88-C(4): 622-629 (2005) | |
| 6 | Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide: A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Transactions 88-C(6): 1332-1342 (2005) | |
| 2001 | ||
| 5 | Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada: Test cost reduction by at-speed BISR for embedded DRAMs. ITC 2001: 182-187 | |
| 1993 | ||
| 4 | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima: Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Design & Test of Computers 10(2): 6-12 (1993) | |
| 1992 | ||
| 3 | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikishi, Katsunori Suma, Kazuyasu Fujishima: A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC 1992: 615-622 | |
| 1989 | ||
| 2 | Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima: A New Array Architecture for Parallel Testing in VLSI Memories. ITC 1989: 322-326 | |
| 1985 | ||
| 1 | Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano: Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC 1985: 451-455 | |
Colors in the list of coauthors
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