Miguel Arias-Estrada

	2012
28		Mario Alberto Mendoza-Barcenas, Eduardo Vizcaino Torres, Esaú Vicente Vivas, Miguel Arias-Estrada, Ignacio Mendoza Nucamendi, Jose Angel Colin Robles: Embedded attitude control system for the educative satellite SATEDU. CONIELECOMP 2012: 118-123
	2009
27		Juan Carlos Moctezuma Eugenio, Miguel Arias-Estrada: Hardware/Software FPGA Architecture for Robotics Applications. ARC 2009: 27-38
26		Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil, Bernard Girau: Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms. IJCNN 2009: 2294-2301
25		Modesto G. Medina-Meléndrez, Miguel Arias-Estrada, Albertina Castro: Input and/or output pruning of composite length FFTs using a DIF-DIT transform decomposition. IEEE Transactions on Signal Processing 57(10): 4124-4128 (2009)
24		Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel Arias-Estrada: Parallel Processor for 3D Recovery from Optical Flow. Int. J. Reconfig. Comp. 2009: (2009)
	2008
23		Cesar Torres-Huitzil, Bernard Girau, Miguel Arias-Estrada: Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity. ICANN (2) 2008: 188-197
22		Rafael Lemuz-López, Miguel Arias-Estrada: Ranking Corner Points by the Angular Difference between Dominant Edges. ICVS 2008: 323-332
21		Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel Arias-Estrada: Parallel Processor for 3D Recovery from Optical Flow. ReConFig 2008: 49-54
20		M. Alejandra Menéndez O., D. Sosa G., Miguel Arias-Estrada, A. Espinosa M., J. E. Lara R.: Creation of a 3D Robot Model and its Integration to a Microsoft Robotics Studio Simulation. SCSS (2) 2008: 143-146
	2007
19		Griselda Saldaña, Miguel Arias-Estrada: Compact FPGA-based systolic array architecture suitable for vision systems. ITNG 2007: 1008-1013
18		Griselda Saldaña, Miguel Arias-Estrada: Compact FPGA-based systolic array architecture suitable for vision systems. IJHPSA 1(2): 124-132 (2007)
	2006
17		Alicia Morales-Reyes, Miguel Arias-Estrada: Stereo Analysis Extension Based on BRDF Reciprocity. CONIELECOMP 2006: 53
16		Rafael Lemuz-López, Miguel Arias-Estrada: Iterative Closest SIFT Formulation for Robust Feature Matching. ISVC (2) 2006: 502-513
15		Rafael Lemuz-López, Miguel Arias-Estrada: A Domain Reduction Algorithm for Incremental Projective Reconstruction. ISVC (2) 2006: 564-575
	2005
14		Gerardo Sosa-Ramirez, Miguel Arias-Estrada: 3D Recovery with Free Hand Camera Motion. ENC 2005: 145-151
13		Liz Castillo-Jimenez, Miguel Arias-Estrada: Super-resolution with integrated radial distortion correction. ENC 2005: 165-173
12		Cesar Torres-Huitzil, Miguel Arias-Estrada: FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing. EURASIP J. Adv. Sig. Proc. 2005(7): 1024-1034 (2005)
	2004
11		Cesar Torres-Huitzil, Miguel Arias-Estrada: Real-time image processing with a compact FPGA-based systolic architecture. Real-Time Imaging 10(3): 177-187 (2004)
	2003
10		Cesar Torres-Huitzil, Miguel Arias-Estrada: Configurable Hardware Architecture for Real-Time Window-Based Image Processing. FPL 2003: 1008-1011
9		Juan M. Xicotencatl, Miguel Arias-Estrada: FPGA Based High Density Spiking Neural Network Array. FPL 2003: 1053-1056
8		Selene Maya-Rueda, Miguel Arias-Estrada: FPGA Processor for Real-Time Optical Flow Computation. FPL 2003: 1103-1106
	2002
7		Miguel Arias-Estrada, Eduardo Rodríguez-Palacios: An FPGA Co-processor for Real-Time Visual Tracking. FPL 2002: 710-719
	2001
6		Miguel Arias-Estrada, Juan M. Xicotencatl: Multiple Stereo Matching Using an Extended Architecture. FPL 2001: 203-212
5		Miguel Arias-Estrada, Cesar Torres-Huitzil: Real-time field programmable gate array architecture for computer vision. J. Electronic Imaging 10(1): 289-296 (2001)
	2000
4		Cesar Torres-Huitzil, Miguel Arias-Estrada: An FPGA Architecture for High Speed Edge and Corner Detection. CAMP 2000: 112-116
3		Selene Maya, Rocio Reynoso, Cesar Torres-Huitzil, Miguel Arias-Estrada: Compact Spiking Neural Network Implementation in FPGA. FPL 2000: 270-276
2		J. J. Vega, M. R. Reynoso, Miguel Arias-Estrada, Leopoldo Altamirano Robles: Bragg Curve Identification Using a Neural Network. IJCNN (4) 2000: 379-382
	1999
1		A. Lecerf, F. Vachon, D. Ouellet, Miguel Arias-Estrada: FPGA Based Computer Vision Camera. FPGA 1999: 248

Coauthor Index

1	Jose Hugo Barron-Zambrano	[21] [24]
2	Fernando Martin del Campo-Ramirez	[21] [24]
3	Liz Castillo-Jimenez	[13]
4	Albertina Castro	[25]
5	Juan Carlos Moctezuma Eugenio	[27]
6	D. Sosa G.	[20]
7	Bernard Girau	[23] [26]
8	A. Lecerf	[1]
9	Rafael Lemuz-López	[15] [16] [22]
10	A. Espinosa M.	[20]
11	Selene Maya	[3]
12	Selene Maya-Rueda	[8]
13	Modesto G. Medina-Meléndrez	[25]
14	Mario Alberto Mendoza-Barcenas	[28]
15	Alicia Morales-Reyes	[17]
16	Ignacio Mendoza Nucamendi	[28]
17	Marco Aurelio Nuño-Maganda	[26]
18	M. Alejandra Menéndez O.	[20]
19	D. Ouellet	[1]
20	J. E. Lara R.	[20]
21	M. R. Reynoso	[2]
22	Rocio Reynoso	[3]
23	Jose Angel Colin Robles	[28]
24	Leopoldo Altamirano Robles	[2]
25	Eduardo Rodríguez-Palacios	[7]
26	Griselda Saldaña	[18] [19]
27	Gerardo Sosa-Ramirez	[14]
28	Eduardo Vizcaino Torres	[28]
29	Cesar Torres-Huitzil	[3] [4] [5] [10] [11] [12] [23] [26]
30	F. Vachon	[1]
31	J. J. Vega	[2]
32	Esaú Vicente Vivas	[28]
33	Juan M. Xicotencatl	[6] [9]

Colors in the list of coauthors

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