 | 2011 |
| 6 |  | Alberto Cicalini,
Sankaran Aniruddhan,
Rahul Apte,
Frederic Bossu,
Ojas Choksi,
Dan Filipovic,
Kunal Godbole,
Tsai-Pi Hung,
Christos Komninakis,
David Maldonado,
Chiewcharn Narathong,
Babak Nejati,
Deirdre O'Shea,
Xiaohong Quan,
Raj Rangarajan,
Janakiram Sankaranarayanan,
Andrew See,
Ravi Sridhara,
Bo Sun,
Wenjun Su,
Klaas van Zalinge,
Gang Zhang,
Kamal Sahota:
A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor.
ISSCC 2011: 368-370 |
| 5 |  | Sankaran Aniruddhan,
Sudip Shekhar,
David J. Allstot:
A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing.
IEEE Trans. on Circuits and Systems 58-I(5): 860-867 (2011) |
| 2006 |
| 4 |  | Sankaran Aniruddhan,
Sudip Shekhar,
David J. Allstot:
A delay generation technique for fast-locking frequency synthesizers.
ISCAS 2006 |
| 3 |  | Sudip Shekhar,
Sankaran Aniruddhan,
David J. Allstot:
A fully-differential CMOS Clapp VCO for IEEE 802.11a applications.
ISCAS 2006 |
| 2005 |
| 2 |  | Sankaran Aniruddhan,
David J. Allstot:
Architectural issues in base-station frequency synthesizers.
ISCAS (6) 2005: 6034-6037 |
| 2004 |
| 1 |  | Sankaran Aniruddhan,
Min Chu,
David J. Allstot:
A lateral-BJT-biased CMOS voltage-controlled oscillator.
ISCAS (1) 2004: 976-979 |