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Hideki Ando Coauthor index pubzone.org

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11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKyohei Yamaguchi, Yuya Kora, Hideki Ando: Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path. ICCD 2011: 313-319
2010
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYusuke Tanaka, Hideki Ando: Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction. IEICE Transactions 93-D(12): 3294-3305 (2010)
2009
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYusuke Tanaka, Hideki Ando: Reducing register file size through instruction pre-execution enhanced by value prediction. ICCD 2009: 238-245
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKazunaga Hyodo, Kengo Iwamoto, Hideki Ando: Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation. IEICE Transactions 92-D(11): 2186-2195 (2009)
2003
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHajime Shimada, Hideki Ando, Toshio Shimada: Pipeline stage unification: a low-energy consumption technique for future mobile processors. ISLPED 2003: 326-329
2002
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRyo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada: A preactivating mechanism for a VT-CMOS cache using address prediction. ISLPED 2002: 247-250
1999
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRyotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata: An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. EUROMICRO 1999: 1432-1440
1998
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya: Software pipelining with path selection. Systems and Computers in Japan 29(9): 74-86 (1998)
1996
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya: Performance Comparison of ILP Machines with Cycle Time Evaluation. ISCA 1996: 213-224
1995
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya: Unconstrained Speculative Execution with Predicated State Buffering. ISCA 1995: 126-137
1993
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya: Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. ICCD 1993: 106-113

Coauthor Index

1Ryo Fujioka [6]
2Tetsuya Hara [1] [2] [3] [4]
3Kazunaga Hyodo [8]
4Kengo Iwamoto [8]
5Mitsuaki Iwata [5]
6Kiyokazu Katayama [6]
7Satoru Kishida [1]
8Ryotaro Kobayashi [5] [6]
9Yuya Kora [11]
10Hirohisa Machida [1]
11Chikako Nakanishi [1] [2] [3] [4]
12Masao Nakaya [1] [2] [3] [4]
13Yukihiro Ogawa [5]
14Hajime Shimada [7]
15Toshio Shimada [5] [6] [7]
16Yusuke Tanaka [9] [10]
17Kyohei Yamaguchi [11]

Colors in the list of coauthors

Last update Sat May 26 04:23:17 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page