Jason Helge Anderson

	2012
34		Warren Wai-Kit Shum, Jason Helge Anderson: Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. FPGA 2012: 107-110
33		Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski: Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA 2012: 111-114
32		Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson: The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86
31		Jason Helge Anderson, Qiang Wang, Chirag Ravishankar: Raising FPGA Logic Density Through Synthesis-Inspired Architecture. IEEE Trans. VLSI Syst. 20(3): 537-550 (2012)
30		Marcel Gort, Jason Helge Anderson: Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. IEEE Trans. on CAD of Integrated Circuits and Systems 31(1): 61-74 (2012)
	2011
29		Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis: Low-cost hardware profiling of run-time and energy in FPGA embedded processors. ASAP 2011: 61-68
28		Jason Helge Anderson, Qiang Wang: Area-efficient FPGA logic elements: Architecture and synthesis. ASP-DAC 2011: 369-375
27		Alireza Rakhshanfar, Jason Helge Anderson: An integer programming placement approach to FPGA clock power reduction. ASP-DAC 2011: 831-836
26		Jason Luu, Jason Helge Anderson, Jonathan Rose: Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA 2011: 227-236
25		Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski: LegUp: high-level synthesis for FPGA-based processor/accelerator systems. FPGA 2011: 33-36
24		Marcel Gort, Jason Helge Anderson: Reducing FPGA Router Run-Time through Algorithm and Architecture. FPL 2011: 336-342
23		Bill Teng, Jason Helge Anderson: Latch-Based Performance Optimization for FPGAs. FPL 2011: 58-63
22		Warren Wai-Kit Shum, Jason Helge Anderson: FPGA glitch power analysis and reduction. ISLPED 2011: 27-32
	2010
21		Jason Helge Anderson: A PUF design for secure FPGA-based embedded systems. ASP-DAC 2010: 1-6
20		Jason Helge Anderson, Chirag Ravishankar: FPGA power reduction by guarded evaluation. FPGA 2010: 157-166
19		Steven Birk, J. Gregory Steffan, Jason Helge Anderson: Parallelizing FPGA placement using Transactional Memory. FPT 2010: 61-69
18		Marcel Gort, Jason Helge Anderson: Deterministic multi-core parallel routing for FPGAs. FPT 2010: 78-86
	2009
17		Jason Helge Anderson: Emerging application domains: research challenges and opportunities for FPGAs. FPGA 2009: 1-2
16		Qiang Wang, Subodh Gupta, Jason Helge Anderson: Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22
15		Jason Helge Anderson, Qiang Wang: Improving logic density through synthesis-inspired architecture. FPL 2009: 105-111
14		Safeen Huda, Muntasir Mallick, Jason Helge Anderson: Clock gating architectures for FPGA power reduction. FPL 2009: 112-118
13		Jason Helge Anderson, Farid N. Najm: Low-Power Programmable FPGA Routing Circuitry. IEEE Trans. VLSI Syst. 17(8): 1048-1060 (2009)
12		Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson: Packing Techniques for Virtex-5 FPGAs. TRETS 2(3): (2009)
	2008
11		Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal: Architecture-specific packing for virtex-5 FPGAs. FPGA 2008: 5-13
	2006
10		Jason Helge Anderson, Farid N. Najm: Active leakage power optimization for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 423-437 (2006)
	2004
9		Jason Helge Anderson, Farid N. Najm: Interconnect capacitance estimation for FPGAs. ASP-DAC 2004: 713-718
8		Jason Helge Anderson, Farid N. Najm, Tim Tuan: Active leakage power optimization for FPGAs. FPGA 2004: 33-41
7		Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng: Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. FPL 2004: 168-178
6		Jason Helge Anderson, Farid N. Najm: Low-power programmable routing circuitry for FPGAs. ICCAD 2004: 602-609
5		Jason Helge Anderson, Farid N. Najm: Power estimation techniques for FPGAs. IEEE Trans. VLSI Syst. 12(10): 1015-1027 (2004)
	2003
4		Jason Helge Anderson, Farid N. Najm: Switching activity analysis and pre-layout activity prediction for FPGAs. SLIP 2003: 15-21
	2000
3		Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman: A Placement Algorithm for FPGA Designs with Multiple I/O Standards. FPL 2000: 211-220
	1998
2		Jason Helge Anderson, Stephen Dean Brown: Technology Mapping for Large Complex PLDs. DAC 1998: 698-703
1		Jason Helge Anderson, Stephen Dean Brown: An LPGA with Foldable PLA-style Logic Blocks. FPGA 1998: 244-252

Coauthor Index

1	Rajat Aggarwal	[11]
2	Taneem Ahmed	[11] [12]
3	Mark Aldham	[25] [29]
4	Steven Birk	[19]
5	Stephen Dean Brown	[1] [2] [25] [29] [33]
6	Andrew Canis	[25] [29] [33]
7	Kamal Chaudhary	[7]
8	Paul Cheng	[7]
9	Jongsok Choi	[25] [33]
10	Tomasz S. Czajkowski	[25] [33]
11	Opal Densmore	[32]
12	Jeffrey Goeders	[32]
13	Marcel Gort	[18] [24] [30]
14	Subodh Gupta	[16]
15	Stefan Hadjis	[33]
16	Safeen Huda	[14]
17	Peter Jamieson (Peter A. Jamieson)	[32]
18	Rajeev Jayaraman	[3]
19	Sandor Kalman	[7]
20	Ahmed Kammoona	[25]
21	Kenneth B. Kent	[32]
22	Paul D. Kundarewich	[11] [12]
23	Jason Luu	[26] [32]
24	Chari Madabhushi	[3] [7]
25	Muntasir Mallick	[14]
26	Sudip Nag	[3] [7]
27	Farid N. Najm	[4] [5] [6] [8] [9] [10] [13]
28	Kevin Nam	[33]
29	Alireza Rakhshanfar	[27]
30	Chirag Ravishankar	[20] [31]
31	Jonathan Rose	[26] [32]
32	Jim Saunders	[3]
33	Warren Wai-Kit Shum	[22] [34]
34	Andrew Somerville	[32]
35	J. Gregory Steffan (John Gregory Steffan)	[19]
36	Brad L. Taylor	[11]
37	Bill Teng	[23]
38	Tim Tuan	[8]
39	Qiang Wang	[15] [16] [28] [31]
40	Chi Wai Yu	[32]
41	Victor Zhang	[25]

Colors in the list of coauthors

Last update Sat May 26 04:23:17 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page