François Anceau

	2011
5		C. Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard: FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FPT 2011: 1-4
4		Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet, Jérôme Juillard: A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors. ISCAS 2011: 2577-2580
3		Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akre, Jérôme Juillard: All-digital PLL array provides reliable distributed clock for SOCs. ISCAS 2011: 2589-2592
2		Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Éric Colinet, Jérôme Juillard: A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation. ISCAS 2011: 2845-2848
	1989
1		François Anceau: Formal Verification: A Significant Step Towards Zero Deffect VLSI Design. IFIP Congress 1989: 528

Coauthor Index

1	Jean-Michel Akre	[3]
2	Éric Colinet	[2] [3] [4] [5]
3	Sylvain Feruglio	[5]
4	Dimitri Galayko	[2] [3] [4] [5]
5	Mohammad Javidan	[2] [3] [4] [5]
6	Jérôme Juillard	[2] [3] [4] [5]
7	Anton Korniienko	[3]
8	Olivier Romain	[5]
9	Gérard Scorletti	[3]
10	C. Shan	[5]
11	Mehdi Terosiet	[5]
12	Eldar Zianbetov	[2] [3] [4] [5]

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