 | 2011 |
| 6 |  | Darren Anand,
Kevin Gorman,
Mark Jacunski,
Adrian Paparelli:
Embedded DRAM in 45-nm Technology and Beyond.
IEEE Design & Test of Computers 28(1): 14-21 (2011) |
| 2010 |
| 5 |  | Mark Jacunski,
Darren Anand,
Robert Busch,
John Fifield,
Matthew Lanahan,
Paul Lane,
Adrian Paparelli,
Gary Pomichter,
Dale Pontius,
Michael Roberge,
Stephen Sliva:
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.
CICC 2010: 1-4 |
| 2004 |
| 4 |  | Michael R. Nelms,
Kevin Gorman,
Darren Anand:
Generating At-Speed Array Fail Maps with Low-Speed ATE.
VTS 2004: 87-96 |
| 2003 |
| 3 |  | Darren Anand,
Bruce Cowan,
Owen Farnsworth,
Peter Jakobsen,
Steven F. Oakland,
Michael Ouellette,
Donald L. Wheater:
An On-Chip Self-Repair Calculation and Fusing Methodology.
IEEE Design & Test of Computers 20(5): 67-75 (2003) |
| 2002 |
| 2 |  | John E. Barth Jr.,
Jeffrey Dreibelbis,
Eric A. Nelson,
Darren Anand,
Gary Pomichter,
Peter Jakobsen,
Michael R. Nelms,
Jeffrey Leach,
George M. Belansek:
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering.
IBM Journal of Research and Development 46(6): 675-690 (2002) |
| 2001 |
| 1 |  | Peter Jakobsen,
Jeffrey Dreibelbis,
Gary Pomichter,
Darren Anand,
John E. Barth Jr.,
Michael R. Nelms,
Jeffrey Leach,
George M. Belansek:
Embedded DRAM built in self test and methodology for test insertion.
ITC 2001: 975-984 |