 | 2011 |
| 16 |  | Alexandre M. Amory,
Luciano Ost,
César A. M. Marcon,
Fernando Gehm Moraes,
Marcelo Lubaszewski:
Evaluating energy consumption of homogeneous MPSoCs using spare tiles.
DATE 2011: 1164-1167 |
| 15 |  | Alexandre M. Amory,
César A. M. Marcon,
Fernando Gehm Moraes,
Marcelo Lubaszewski:
Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.
International Symposium on Rapid System Prototyping 2011: 164-170 |
| 14 |  | Alexandre M. Amory,
Cristiano Lazzari,
Marcelo Lubaszewski,
Fernando Gehm Moraes:
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.
J. Parallel Distrib. Comput. 71(5): 675-686 (2011) |
| 2009 |
| 13 |  | Alzemiro H. Lucas,
Alexandre M. Amory,
Fernando Gehm Moraes:
Crosstalk Fault Tolerant NoC: Design and Evaluation.
VLSI-SoC 2009: 81-93 |
| 2008 |
| 12 |  | Érika F. Cota,
Fernanda Gusmão de Lima Kastensmidt,
Maico Cassel,
Marcos Herve,
Pedro Almeida,
Paulo Meirelles,
Alexandre M. Amory,
Marcelo Lubaszewski:
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers 57(9): 1202-1215 (2008) |
| 2007 |
| 11 |  | Érika F. Cota,
Fernanda Lima Kastensmidt,
Maico Cassel,
Paulo Meirelles,
Alexandre M. Amory,
Marcelo Lubaszewski:
Redefining and testing interconnect faults in Mesh NoCs.
ITC 2007: 1-10 |
| 10 |  | Alexandre M. Amory,
Frederico Ferlini,
Marcelo Lubaszewski,
Fernando Moraes:
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.
VTS 2007: 435-440 |
| 9 |  | Alexandre M. Amory,
Marcelo Lubaszewski,
Fernando Gehm Moraes,
Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
CoRR abs/0710.4795: (2007) |
| 8 |  | Alexandre M. Amory,
Kees Goossens,
Erik Jan Marinissen,
Marcelo Lubaszewski,
Fernando Moraes:
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Computers & Digital Techniques 1(3): 197-206 (2007) |
| 2006 |
| 7 |  | Alexandre M. Amory,
Kees Goossens,
Erik Jan Marinissen,
Marcelo Lubaszewski,
Fernando Moraes:
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
European Test Symposium 2006: 213-218 |
| 2005 |
| 6 |  | Alexandre M. Amory,
Marcelo Lubaszewski,
Fernando Gehm Moraes,
Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
DATE 2005: 62-63 |
| 5 |  | Alexandre M. Amory,
Eduardo Wenzel Brião,
Érika F. Cota,
Marcelo Lubaszewski,
Fernando Gehm Moraes:
A scalable test strategy for network-on-chip routers.
ITC 2005: 9 |
| 2004 |
| 4 |  | Alexandre M. Amory,
Érika F. Cota,
Marcelo Lubaszewski,
Fernando Gehm Moraes:
Reducing test time with processor reuse in network-on-chip based systems.
SBCCI 2004: 111-116 |
| 2003 |
| 3 |  | Alexandre M. Amory,
Leandro A. Oliveira,
Fernando Gehm Moraes:
Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures.
VLSI-SOC 2003: 174-179 |
| 2000 |
| 2 |  | Fabian Vargas,
Alexandre M. Amory:
Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.
Asian Test Symposium 2000: 417-422 |
| 1 |  | Fabian Vargas,
Alexandre M. Amory,
Raoul Velazco:
Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL.
IOLTW 2000: 67-72 |