 | 2012 |
| 12 |  | Kambiz Kaviani,
Amir Amirkhany,
Charlie Huang,
Phuong Le,
Chris Madden,
Keisuke Saito,
Koji Sano,
Vinod Murugan,
Wendemagegnehu T. Beyene,
Ken Chang,
Chuck Yuan:
A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration.
ISSCC 2012: 132-134 |
| 11 |  | Amir Amirkhany,
Kambiz Kaviani,
Ali-Azam Abbasfar,
H. Md. Shuaeb Fazeel,
Wendemagegnehu T. Beyene,
Chikara Hoshino,
Chris Madden,
Ken Chang,
Chuck Yuan:
A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link.
ISSCC 2012: 138-140 |
| 10 |  | Amir Amirkhany,
Jason Wei,
Navin K. Mishra,
Jie Shen,
Wendemagegnehu T. Beyene,
Catherine Chen,
T. J. Chin,
Deborah Dressler,
Charlie Huang,
Vijay P. Gadde,
Mohammad Hekmat,
Kambiz Kaviani,
Hai Lan,
Phuong Le,
Mahabaleshwara,
Chris Madden,
Sanku Mukherjee,
Leneesh Raghavan,
Keisuke Saito,
Dave Secker,
Arul Sendhil,
Ralf Schmitt,
H. Md. Shuaeb Fazeel,
Gundlapalli Shanmukha Srinivas,
Ting Wu,
Chanh Tran,
Arun Vaidyanath,
Kapil Vyas,
Ling Yang,
Manish Jain,
Kun-Yung Ken Chang,
Xingchao Yuan:
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
J. Solid-State Circuits 47(4): 911-925 (2012) |
| 9 |  | Kambiz Kaviani,
Ting Wu,
Jason Wei,
Amir Amirkhany,
Jie Shen,
T. J. Chin,
Chintan Thakkar,
Wendemagegnehu T. Beyene,
Norman Chan,
Catherine Chen,
Bing Ren Chuang,
Deborah Dressler,
Vijay P. Gadde,
Mohammad Hekmat,
Eugene Ho,
Charlie Huang,
Phuong Le,
Mahabaleshwara,
Chris Madden,
Navin K. Mishra,
Leneesh Raghavan,
Keisuke Saito,
Ralf Schmitt,
Dave Secker,
Xudong Shi,
H. Md. Shuaeb Fazeel,
Gundlapalli Shanmukha Srinivas,
Steve Zhang,
Chanh Tran,
Arun Vaidyanath,
Kapil Vyas,
Manish Jain,
Kun-Yung Ken Chang,
Xingchao Yuan:
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
J. Solid-State Circuits 47(4): 926-937 (2012) |
| 2011 |
| 8 |  | Navin K. Mishra,
Manish Jain,
Phuong Le,
Sanku Mukherjee,
Arul Sendhil,
Amir Amirkhany:
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.
CICC 2011: 1-4 |
| 7 |  | John C. Eble,
Scott Best,
Brian S. Leibowitz,
Lei Luo,
Robert Palmer,
John Wilson,
Jared Zerbe,
Amir Amirkhany,
Nhat Nguyen:
Power-efficient I/O design considerations for high-bandwidth applications.
CICC 2011: 1-8 |
| 2010 |
| 6 |  | Farshid Aryanfar,
Amir Amirkhany:
A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces.
IEEE Trans. on Circuits and Systems 57-II(5): 339-342 (2010) |
| 5 |  | Mahmoud Reza Ahmadi,
Amir Amirkhany,
Ramesh Harjani:
A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links.
J. Solid-State Circuits 45(8): 1533-1541 (2010) |
| 2009 |
| 4 |  | Mahmoud Reza Ahmadi,
Amir Amirkhany,
Ramesh Harjani:
A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links.
CICC 2009: 125-128 |
| 2007 |
| 3 |  | Jafar Savoj,
Ali-Azam Abbasfar,
Amir Amirkhany,
Bruno W. Garlepp,
Mark A. Horowitz:
A new technique for characterization of digital-to-analog converters in high-speed systems.
DATE 2007: 433-438 |
| 2 |  | Amir Amirkhany,
Ali-Azam Abbasfar,
Vladimir Stojanovic,
Mark A. Horowitz:
Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links.
ICC 2007: 2693-2698 |
| 2006 |
| 1 |  | Amir Amirkhany,
Ali-Azam Abbasfar,
Vladimir Stojanovic,
Mark A. Horowitz:
Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links.
GLOBECOM 2006 |