A. Amirabadi

	2007
7		A. Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani: Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. IEEE Trans. VLSI Syst. 15(2): 125-134 (2007)
	2006
6		S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha: Double edge triggered Feedback Flip-Flop in sub 100NM technology. ASP-DAC 2006: 297-302
5		A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha: Low power and high performance clock delayed domino logic using saturated keeper. ISCAS 2006
4		A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha: Low power low leakage clock gated static pulsed flip-flop. ISCAS 2006
3		A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha: Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. ISVLSI 2006: 373-377
	2005
2		A. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani: Domino logic with an efficient variable threshold voltage keeper. ISCAS (2) 2005: 1674-1677
	2004
1		A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz: Leakage current reduction by new technique in standby mode. ACM Great Lakes Symposium on VLSI 2004: 158-161

Coauthor Index

1	Ali Afzali-Kusha	[1] [2] [3] [4] [5] [6] [7]
2	A. Chehelcheraghi	[5]
3	Javid Jaffari	[1]
4	Ali Khaki-Firooz	[1]
5	Nariman Moezzi Madani	[2]
6	Y. Mortazavi	[2] [7]
7	Mehrdad Nourani	[1] [2] [7]
8	S. H. Rasouli	[3] [4] [5] [6]
9	A. Seyedi	[5] [6]
10	A. S. Seyedi	[3] [4]

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