Ajith Amerasekera

	2010
4		Ajith Amerasekera: Ultra low power electronics in the next decade. ISLPED 2010: 237-238
	2008
3		Ajith Amerasekera: The Changing Design Landscape. IEEE Design & Test of Computers 25(4): 333 (2008)
	2007
2		Ajith Amerasekera: Concurrent Optimization of Technology and Design for Nano CMOS. VLSI Design 2007: 27
	2002
1		Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun: A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED 2002: 148-

Coauthor Index

1	Baher Haroun	[1]
2	Bob Helmick	[1]
3	Richard Jennings	[1]
4	Prasun Raha	[1]
5	Scott Randall	[1]

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