![]() | ![]() |
| 1995 | ||
|---|---|---|
| 1 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi: A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging. VLSI Design 1995: 398-402 | |
| 1 | Keshab K. Parhi | [1] |
| 2 | Hosahalli R. Srinivas | [1] |
Data released under the ODC-BY 1.0 license — See also our legal information page