 | 2012 |
| 19 |  | Adam Makosiej,
Olivier Thomas,
Andrei Vladimirescu,
Amara Amara:
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization.
DATE 2012: 93-98 |
| 2011 |
| 18 |  | Islam Seoudi,
Karima Amara,
Fabrice Gayral,
Renzo Dal Molin,
Amara Amara:
Multi-electrode system for pacemaker applications.
ICECS 2011: 125-128 |
| 2010 |
| 17 |  | Amara Amara,
Bastien Giraud,
Olivier Thomas:
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.
DELTA 2010: 241-244 |
| 16 |  | Olivier Thomas,
J.-P. Noel,
Claire Fenouillet-Béranger,
M.-A. Jaud,
J. Dura,
P. Perreau,
F. Boeuf,
François Andrieu,
D. Delprat,
F. Boedt,
Konstantin Bourdelle,
Bich-Yen Nguyen,
Andrei Vladimirescu,
Amara Amara:
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.
ISCAS 2010: 1703-1706 |
| 15 |  | Motoi Ichihashi,
Hélène Lhermet,
Edith Beigné,
Frédéric Rothan,
Marc Belleville,
Amara Amara:
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process.
J. Low Power Electronics 6(1): 201-210 (2010) |
| 2009 |
| 14 |  | Piotr Nasalski,
Adam Makosiej,
Bastien Giraud,
Andrei Vladimirescu,
Amara Amara:
SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch.
ISCAS 2009: 3170-3173 |
| 13 |  | Motoi Ichihashi,
Hélène Lhermet,
Edith Beigné,
Frédéric Rothan,
Marc Belleville,
Amara Amara:
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process.
PATMOS 2009: 336-346 |
| 2008 |
| 12 |  | Bastien Giraud,
Amara Amara:
Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.
DELTA 2008: 201-204 |
| 11 |  | Bastien Giraud,
Amara Amara:
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology.
ISCAS 2008: 1906-1909 |
| 2007 |
| 10 |  | Bastien Giraud,
Amara Amara,
Andrei Vladimirescu:
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.
ISCAS 2007: 3022-3025 |
| 2006 |
| 9 |  | Amara Amara,
Frederic Amiel,
Thomas Ea:
FPGA vs. ASIC for low power applications.
Microelectronics Journal 37(8): 669-677 (2006) |
| 2005 |
| 8 |  | Florence Rossant,
Frederic Amiel,
Thomas Ea,
Amara Amara,
Manuel Torres Eslava:
Iris identification and robustness evaluation of a wavelet packets based algorithm.
ICIP (3) 2005: 257-260 |
| 7 |  | Olivier Thomas,
Amara Amara:
Ultra low voltage design considerations of SOI SRAM memory cells.
ISCAS (4) 2005: 4094-4097 |
| 2004 |
| 6 |  | Erik Rydgren,
Thomas Ea,
Frederic Amiel,
Florence Rossant,
Amara Amara:
IRIS features extraction using wavelet packets.
ICIP 2004: 861-864 |
| 5 |  | Jean-François Naviner,
Amara Amara:
Systems-on-chip for telecommunications.
Annales des Télécommunications 59(7-8): 755-758 (2004) |
| 4 |  | Alexandre Valentian,
Olivier Thomas,
Andrei Vladimirescu,
Amara Amara:
Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. VLSI Syst. 12(6): 662-669 (2004) |
| 2003 |
| 3 |  | Olivier Thomas,
Amara Amara:
An SOI 4 transistors self-refresh ultra-low-voltage memory cell.
ISCAS (5) 2003: 401-404 |
| 2001 |
| 2 |  | A. Turier,
L. Ben Ammar,
Amara Amara:
Static power consumption management in CMOS memories.
ISCAS (4) 2001: 506-509 |
| 1996 |
| 1 |  | Philippe Royannez,
Amara Amara:
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm.
Great Lakes Symposium on VLSI 1996: 24-28 |