Motoki Amagasaki

	2012
20		Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi: COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Transactions 95-D(2): 294-302 (2012)
19		Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: An Easily Testable Routing Architecture and Prototype Chip. IEICE Transactions 95-D(2): 303-313 (2012)
	2011
18		Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: An Easily Testable Routing Architecture and Efficient Test Technique. FPL 2011: 291-294
17		Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi: An easily testable routing architecture of FPGA. VLSI-SoC 2011: 106-109
16		Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. Embedded Systems Letters 3(3): 89-92 (2011)
15		Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Transactions 94-C(4): 548-556 (2011)
14		Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: Parallelization of the channel width search for FPGA routing. SIGARCH Computer Architecture News 39(4): 82-85 (2011)
	2010
13		Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM 2010: 47-54
12		Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. FPL 2010: 298-303
11		Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. FPL 2010: 304-309
10		Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A robust reconfigurable logic device based on less configuration memory logic cell. FPT 2010: 162-169
9		Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Power-aware FPGA routing fabrics and design tools. VLSI-SoC 2010: 67-72
8		Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. TRETS 4(1): 5 (2010)
	2009
7		Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi: Memory Sharing Approach for TMR Softcore Processor. ARC 2009: 268-274
6		Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC 2009: 97-109
5		Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi: A novel states recovery technique for the TMR softcore processor. FPL 2009: 543-546
	2008
4		Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi: An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. Int. J. Reconfig. Comp. 2008: (2008)
	2007
3		Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi: Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC 2007: 142-154
2		Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi: A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. FPL 2007: 550-553
	2006
1		Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi: Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. VLSI-SoC 2006: 198-203

Coauthor Index

1	Jyunya Eto	[9]
2	Naoto Hamabe	[1]
3	Yoshinobu Ichida	[12] [15] [19]
4	Yoshihiro Ichinomiya	[5] [7] [10] [11] [13] [16]
5	Jun Iida	[12] [15] [19]
6	Masahiro Iida	[1] [2] [3] [4] [6] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
7	Kazuki Inoue	[6] [8] [15] [17] [18] [19]
8	Tomoyuki Ishida	[5] [7]
9	Masahiro Koga	[4] [12] [15] [19]
10	Morihiro Kuga	[5] [7] [9] [13] [14]
11	Kazunori Matsuyama	[1] [2] [3]
12	Hideaki Nakayama	[1] [3]
13	Shoichi Nishida	[9]
14	Yasuhiro Okamoto	[8] [10] [11] [20]
15	Mitsuro Saji	[12] [15] [19]
16	Hiroomi Sawada	[14]
17	Takurou Shimokawa	[1]
18	Toshinori Sueyoshi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
19	Shiro Tanoue	[5] [7] [13]
20	Ryoichi Yamaguchi	[1] [2] [3] [4]
21	Hiroki Yosho	[8] [18]
22	Qian Zhao	[8] [10] [16] [20]

Last update Sat May 26 04:23:17 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page