 | 2012 |
|---|
| 111 |       | Xing Wei,
Wai-Chung Tang,
Yu-Liang Wu,
Cliff C. N. Sze,
Charles J. Alpert:
WRIP: logic restructuring techniques for wirelength-driven incremental placement.
ACM Great Lakes Symposium on VLSI 2012: 327-332 |
| 110 | | Myung-Chul Kim,
Natarajan Viswanathan,
Charles J. Alpert,
Igor L. Markov,
Shyam Ramji:
MAPLE: multilevel adaptive placement for mixed-size designs.
ISPD 2012: 193-200 |
| 109 | | Samuel I. Ward,
Myung-Chul Kim,
Natarajan Viswanathan,
Zhuo Li,
Charles J. Alpert,
Earl E. Swartzlander Jr.,
David Z. Pan:
Keep it straight: teaching placement how to better handle designs with datapaths.
ISPD 2012: 79-86 |
| 2011 |
|---|
| 108 | | Natarajan Viswanathan,
Charles J. Alpert,
Cliff C. N. Sze,
Zhuo Li,
Gi-Joon Nam,
Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite.
ISPD 2011: 141-146 |
| 107 | | Samuel I. Ward,
David A. Papa,
Zhuo Li,
Cliff N. Sze,
Charles J. Alpert,
Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs.
ISPD 2011: 91-98 |
| 106 | | David A. Papa,
Charles J. Alpert,
Cliff C. N. Sze,
Zhuo Li,
Natarajan Viswanathan,
Gi-Joon Nam,
Igor L. Markov:
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.
IEEE Micro 31(4): 51-62 (2011) |
| 105 | | Ying Zhou,
Charles J. Alpert,
Zhuo Li,
Cliff N. Sze,
Louise Trevillyan:
Shedding Physical Synthesis Area Bloat.
VLSI Design 2011: (2011) |
| 2010 |
|---|
| 104 | | Tanuj Jindal,
Charles J. Alpert,
Jiang Hu,
Zhuo Li,
Gi-Joon Nam,
Charles B. Winn:
Detecting tangled logic structures in VLSI netlists.
DAC 2010: 603-608 |
| 103 | | Taraneh Taghavi,
Zhuo Li,
Charles J. Alpert,
Gi-Joon Nam,
Andrew Huber,
Shyam Ramji:
New placement prediction and mitigation techniques for local routing congestion.
ICCAD 2010: 621-624 |
| 102 | | Yi-Lin Chuang,
Gi-Joon Nam,
Charles J. Alpert,
Yao-Wen Chang,
Jarrod A. Roy,
Natarajan Viswanathan:
Design-hierarchy aware mixed-size placement for routability optimization.
ICCAD 2010: 663-668 |
| 101 | | Charles J. Alpert,
Zhuo Li,
Michael D. Moffitt,
Gi-Joon Nam,
Jarrod A. Roy,
Gustavo Tellez:
What makes a design difficult to route.
ISPD 2010: 7-12 |
| 100 | | Zhuo Li,
David A. Papa,
Charles J. Alpert,
Shiyan Hu,
Weiping Shi,
Cliff C. N. Sze,
Ying Zhou:
Ultra-fast interconnect driven cell cloning for minimizing critical path delay.
ISPD 2010: 75-82 |
| 99 | | Natarajan Viswanathan,
Gi-Joon Nam,
Jarrod A. Roy,
Zhuo Li,
Charles J. Alpert,
Shyam Ramji,
Chris Chu:
ITOP: integrating timing optimization within placement.
ISPD 2010: 83-90 |
| 98 | | David A. Papa,
Michael D. Moffitt,
Charles J. Alpert,
Igor L. Markov:
Speeding Up Physical Synthesis with Transactional Timing Analysis.
IEEE Design & Test of Computers 27(5): 14-25 (2010) |
| 2009 |
|---|
| 97 | | Shiyan Hu,
Zhuo Li,
Charles J. Alpert:
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.
DAC 2009: 424-429 |
| 96 | | Jarrod A. Roy,
Natarajan Viswanathan,
Gi-Joon Nam,
Charles J. Alpert,
Igor L. Markov:
CRISP: Congestion reduction by iterated spreading during placement.
ICCAD 2009: 357-362 |
| 95 | | Cliff N. Sze,
Phillip Restle,
Gi-Joon Nam,
Charles J. Alpert:
Ispd2009 clock network synthesis contest.
ISPD 2009: 149-150 |
| 94 | | Shiyan Hu,
Zhuo Li,
Charles J. Alpert:
A faster approximation scheme for timing driven minimum cost layer assignment.
ISPD 2009: 167-174 |
| 93 | | Shiyan Hu,
Zhuo Li,
Charles J. Alpert:
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment.
IEEE Trans. on Circuits and Systems 56-II(7): 580-584 (2009) |
| 2008 |
|---|
| 92 | | Michael D. Moffitt,
David A. Papa,
Zhuo Li,
Charles J. Alpert:
Path smoothing via discrete optimization.
DAC 2008: 724-727 |
| 91 | | Shiyan Hu,
Zhuo Li,
Charles J. Alpert:
A polynomial time approximation scheme for timing constrained minimum cost layer assignment.
ICCAD 2008: 112-115 |
| 90 | | Tao Luo,
David A. Papa,
Zhuo Li,
Chin-Ngai Sze,
Charles J. Alpert,
David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement.
ICCAD 2008: 204-211 |
| 89 | | David A. Papa,
Tao Luo,
Michael D. Moffitt,
Chin-Ngai Sze,
Zhuo Li,
Gi-Joon Nam,
Charles J. Alpert,
Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.
ISPD 2008: 2-9 |
| 88 | | Zhuo Li,
Charles J. Alpert,
Shiyan Hu,
Tuhin Muhmud,
Stephen T. Quay,
Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment.
ISPD 2008: 71-77 |
| 87 | | David A. Papa,
Tao Luo,
Michael D. Moffitt,
Chin-Ngai Sze,
Zhuo Li,
Gi-Joon Nam,
Charles J. Alpert,
Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2156-2168 (2008) |
| 2007 |
|---|
| 86 | | Haoxing Ren,
David Z. Pan,
Charles J. Alpert,
Gi-Joon Nam,
Paul G. Villarrubia:
Hippocrates: First-Do-No-Harm Detailed Placement.
ASP-DAC 2007: 141-146 |
| 85 | | Shrirang K. Karandikar,
Charles J. Alpert,
Mehmet Can Yildiz,
Paul Villarrubia,
Stephen T. Quay,
T. Mahmud:
Fast Electrical Correction Using Resizing and Buffering.
ASP-DAC 2007: 553-558 |
| 84 | | Natarajan Viswanathan,
Gi-Joon Nam,
Charles J. Alpert,
Paul Villarrubia,
Haoxing Ren,
Chris C. N. Chu:
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
DAC 2007: 453-458 |
| 83 | | Charles J. Alpert,
Chris C. N. Chu,
Paul G. Villarrubia:
The coming of age of physical synthesis.
ICCAD 2007: 246-249 |
| 82 | | Zhuo Li,
Charles J. Alpert,
Stephen T. Quay,
Sachin S. Sapatnekar,
Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages.
ISQED 2007: 841-846 |
| 81 | | Charles J. Alpert,
Shrirang K. Karandikar,
Zhuo Li,
Gi-Joon Nam,
Stephen T. Quay,
Haoxing Ren,
Cliff C. N. Sze,
Paul G. Villarrubia,
Mehmet Can Yildiz:
The nuts and bolts of physical synthesis.
SLIP 2007: 89-94 |
| 80 | | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Chin-Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007) |
| 79 | | Haoxing Ren,
David Z. Pan,
Charles J. Alpert,
Paul G. Villarrubia,
Gi-Joon Nam:
Diffusion-Based Placement Migration With Application on Legalization.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2158-2172 (2007) |
| 78 | | Chin-Ngai Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Path-Based Buffer Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1346-1355 (2007) |
| 2006 |
|---|
| 77 | | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering.
DAC 2006: 308-313 |
| 76 | | Charles J. Alpert,
Andrew B. Kahng,
Cliff C. N. Sze,
Qinke Wang:
Timing-driven Steiner trees are (practically) free.
DAC 2006: 389-392 |
| 75 | | Gi-Joon Nam,
Sherief Reda,
Charles J. Alpert,
Paul Villarrubia,
Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 678-691 (2006) |
| 74 | | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006) |
| 2005 |
|---|
| 73 | | Charles J. Alpert,
Gi-Joon Nam,
Paul Villarribua,
Mehmet Can Yildiz:
Placement stability metrics.
ASP-DAC 2005: 1144-1147 |
| 72 | | Zhuo Li,
Cliff C. N. Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Making fast buffer insertion even faster via approximation techniques.
ASP-DAC 2005: 13-18 |
| 71 | | Cliff C. N. Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Path based buffer insertion.
DAC 2005: 509-514 |
| 70 | | Haoxing Ren,
David Zhigang Pan,
Charles J. Alpert,
Paul Villarrubia:
Diffusion-based placement migration.
DAC 2005: 515-520 |
| 69 |  | Tao Luo,
Haoxing Ren,
Charles J. Alpert,
David Zhigang Pan:
Computational geometry based placement migration.
ICCAD 2005: 41-47 |
| 68 | | Ganesh Venkataraman,
Nikhil Jayakumar,
Jiang Hu,
Peng Li,
Sunil P. Khatri,
Anand Rajaram,
Patrick McGuinness,
Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks.
ICCAD 2005: 592-596 |
| 67 | | Charles J. Alpert,
Andrew B. Kahng,
Gi-Joon Nam,
Sherief Reda,
Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement.
ISPD 2005: 200-207 |
| 66 | | Gi-Joon Nam,
Charles J. Alpert,
Paul Villarrubia,
Bruce Winter,
Mehmet Can Yildiz:
The ISPD2005 placement contest and benchmark suite.
ISPD 2005: 216-220 |
| 65 | | Rajeev R. Rao,
David Blaauw,
Dennis Sylvester,
Charles J. Alpert,
Sani R. Nassif:
An efficient surface-based low-power buffer insertion algorithm.
ISPD 2005: 86-93 |
| 2004 |
|---|
| 64 | | Charles J. Alpert,
Patrick Groeneveld:
Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004
ACM 2004 |
| 63 | | Cliff C. N. Sze,
Jiang Hu,
Charles J. Alpert:
A place and route aware buffered Steiner tree construction.
ASP-DAC 2004: 355-360 |
| 62 | | Weiping Shi,
Zhuo Li,
Charles J. Alpert:
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost.
ASP-DAC 2004: 609-614 |
| 61 | | Charles J. Alpert,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment.
DAC 2004: 24-29 |
| 60 | | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan.
ICCAD 2004: 706-711 |
| 59 | | Charles J. Alpert,
Milos Hrkic,
Stephen T. Quay:
A fast algorithm for identifying good buffer insertion candidate locations.
ISPD 2004: 47-52 |
| 58 | | Charles J. Alpert,
Chris C. N. Chu,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Chandramouli V. Kashyap,
Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004) |
| 57 | | Charles J. Alpert,
Frank Liu,
Chandramouli V. Kashyap,
Anirudh Devgan:
Closed-form delay and slew metrics made easy.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1661-1669 (2004) |
| 56 | | Frank Liu,
Chandramouli V. Kashyap,
Charles J. Alpert:
A delay metric for RC circuits based on the Weibull distribution.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 443-447 (2004) |
| 55 | | Chandramouli V. Kashyap,
Charles J. Alpert,
Frank Liu,
Anirudh Devgan:
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 509-516 (2004) |
| 54 | | Charles J. Alpert,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay,
Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004) |
| 2003 |
|---|
| 53 | | Massoud Pedram,
Charles J. Alpert:
Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003
ACM 2003 |
| 52 | | Charles J. Alpert,
Frank Liu,
Chandramouli V. Kashyap,
Anirudh Devgan:
Delay and slew metrics using the lognormal distribution.
DAC 2003: 382-385 |
| 51 | | Charles J. Alpert,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay:
Porosity aware buffered steiner tree construction.
ISPD 2003: 158-165 |
| 50 | | Chandramouli V. Kashyap,
Charles J. Alpert,
Frank Liu,
Anirudh Devgan:
Closed form expressions for extending step delay and slew metrics to ramp inputs.
ISPD 2003: 24-31 |
| 49 | | Charles J. Alpert,
Gi-Joon Nam,
Paul G. Villarrubia:
Effective free space management for cut-based placement via analytical constraint generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1343-1353 (2003) |
| 48 | | Soha Hassoun,
Charles J. Alpert:
Optimal path routing in single- and multiple-clock domain systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1580-1588 (2003) |
| 47 | | Charles J. Alpert,
Andrew B. Kahng,
Bao Liu,
Ion I. Mandoiu,
Alexander Zelikovsky:
Minimum buffered routing with bounded capacitive load for slew rate and reliability control.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 241-253 (2003) |
| 46 | | Charles J. Alpert,
Sachin S. Sapatnekar:
Guest editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 385-386 (2003) |
| 45 | | Jiang Hu,
Charles J. Alpert,
Stephen T. Quay,
Gopal Gandham:
Buffer insertion with adaptive blockage avoidance.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 492-498 (2003) |
| 44 | | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003) |
| 2002 |
|---|
| 43 | | David P. LaPotin,
Charles J. Alpert,
John Lillis:
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002
ACM 2002 |
| 42 | | Soha Hassoun,
Charles J. Alpert,
Meera Thiagarajan:
Optimal buffered routing path constructions for single and multiple clock domain systems.
ICCAD 2002: 247-253 |
| 41 | | Frank Liu,
Chandramouli V. Kashyap,
Charles J. Alpert:
A delay metric for RC circuits based on the Weibull distribution.
ICCAD 2002: 620-624 |
| 40 | | Charles J. Alpert,
Gi-Joon Nam,
Paul Villarrubia:
Free space management for cut-based placement.
ICCAD 2002: 746-751 |
| 39 | | Charles J. Alpert,
Chris C. N. Chu,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Chandramouli V. Kashyap,
Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
ISPD 2002: 104-109 |
| 38 | | Jiang Hu,
Charles J. Alpert,
Stephen T. Quay,
Gopal Gandham:
Buffer insertion with adaptive blockage avoidance.
ISPD 2002: 92-97 |
| 37 | | Chandramouli V. Kashyap,
Charles J. Alpert,
Frank Liu,
Anirudh Devgan:
PERI: a technique for extending delay and slew metrics to ramp inputs.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 57-62 |
| 36 | | Charles J. Alpert,
Anirudh Devgan,
John P. Fishburn,
Stephen T. Quay:
Correction to "interconnect synthesis without wire tapering".
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 497-497 (2002) |
| 35 | | Suresh Raman,
Sachin S. Sapatnekar,
Charles J. Alpert:
Probability-driven routing in a datapath environment.
Integration 31(2): 159-182 (2002) |
| 2001 |
|---|
| 34 | | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation.
DAC 2001: 189-194 |
| 33 | | Charles J. Alpert,
Andrew B. Kahng,
Bao Liu,
Ion I. Mandoiu,
Alexander Zelikovsky:
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control.
ICCAD 2001: 408- |
| 32 | | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays.
ISCAS (5) 2001: 399-402 |
| 31 | | Charles J. Alpert,
Milos Hrkic,
Jiang Hu,
Andrew B. Kahng,
John Lillis,
Bao Liu,
Stephen T. Quay,
Sachin S. Sapatnekar,
A. J. Sullivan,
Paul Villarrubia:
Buffered Steiner trees for difficult instances.
ISPD 2001: 4-9 |
| 30 | | Charles J. Alpert,
Anirudh Devgan,
John P. Fishburn,
Stephen T. Quay:
Interconnect synthesis without wire tapering.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 90-104 (2001) |
| 29 | | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001) |
| 28 | | Charles J. Alpert,
Anirudh Devgan,
Chandramouli V. Kashyap:
RC delay metrics for performance optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 571-582 (2001) |
| 2000 |
|---|
| 27 | | Chandramouli V. Kashyap,
Charles J. Alpert,
Anirudh Devgan:
An "Effective" Capacitance Based Delay Metric for RC Interconnect.
ICCAD 2000: 229-234 |
| 26 | | Suresh Raman,
Sachin S. Sapatnekar,
Charles J. Alpert:
Datapath routing based on a decongestion metric.
ISPD 2000: 122-127 |
| 25 | | Charles J. Alpert,
Anirudh Devgan,
Chandramouli V. Kashyap:
A two moment RC delay metric for performance optimization.
ISPD 2000: 69-74 |
| 24 | | Charles J. Alpert,
Andrew E. Caldwell,
Andrew B. Kahng,
Igor L. Markov:
Hypergraph partitioning with fixed vertices [VLSI CAD].
IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 267-272 (2000) |
| 1999 |
|---|
| 23 | | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Buffer Insertion with Accurate Gate and Interconnect Delay Computation.
DAC 1999: 479-484 |
| 22 | | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Is wire tapering worthwhile?
ICCAD 1999: 430-436 |
| 21 | | Charles J. Alpert,
Andrew E. Caldwell,
Andrew B. Kahng,
Igor L. Markov:
Partitioning with terminals: a "new" problem and new benchmarks.
ISPD 1999: 151-157 |
| 20 | | Charles J. Alpert,
Andrew B. Kahng,
So-Zen Yao:
Spectral Partitioning with Multiple Eigenvectors.
Discrete Applied Mathematics 90(1-3): 3-26 (1999) |
| 19 | | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Buffer insertion for noise and delay optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1633-1645 (1999) |
| 1998 |
|---|
| 18 | | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Buffer Insertion for Noise and Delay Optimization.
DAC 1998: 362-367 |
| 17 | | Charles J. Alpert:
The ISPD98 circuit benchmark suite.
ISPD 1998: 80-85 |
| 16 | | Charles J. Alpert,
Tony F. Chan,
Andrew B. Kahng,
Igor L. Markov,
Pep Mulet:
Faster minimization of linear wirelength for global placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 3-13 (1998) |
| 15 | | Charles J. Alpert,
Jen-Hsin Huang,
Andrew B. Kahng:
Multilevel circuit partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 655-667 (1998) |
| 1997 |
|---|
| 14 | | Charles J. Alpert,
Jen-Hsin Huang,
Andrew B. Kahng:
Multilevel Circuit Partitioning.
DAC 1997: 530-533 |
| 13 | | Charles J. Alpert,
Anirudh Devgan:
Wire Segmenting for Improved Buffer Insertion.
DAC 1997: 588-593 |
| 12 | | Charles J. Alpert,
Tony F. Chan,
Dennis J.-H. Huang,
Igor L. Markov,
Kenneth Yan:
Quadratic Placement Revisited.
DAC 1997: 752-757 |
| 11 | | Charles J. Alpert,
Tony F. Chan,
Dennis J.-H. Huang,
Andrew B. Kahng,
Igor L. Markov,
Pep Mulet,
Kenneth Yan:
Faster minimization of linear wirelength for global placement.
ISPD 1997: 4-11 |
| 1996 |
|---|
| 10 | | Charles J. Alpert,
Andrew B. Kahng:
A general framework for vertex orderings with applications to circuit clustering.
IEEE Trans. VLSI Syst. 4(2): 240-246 (1996) |
| 1995 |
|---|
| 9 | | Charles J. Alpert,
So-Zen Yao:
Spectral Partitioning: The More Eigenvectors, The Better.
DAC 1995: 195-200 |
| 8 | | Charles J. Alpert,
Andrew B. Kahng:
Multiway partitioning via geometric embeddings, orderings, and dynamic programming.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1342-1358 (1995) |
| 7 | | Charles J. Alpert,
T. C. Hu,
Dennis J.-H. Huang,
Andrew B. Kahng,
David R. Karger:
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 890-896 (1995) |
| 6 | | Charles J. Alpert,
Andrew B. Kahng:
Recent directions in netlist partitioning: a survey.
Integration 19(1-2): 1-81 (1995) |
| 1994 |
|---|
| 5 | | Charles J. Alpert,
Andrew B. Kahng:
Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming.
DAC 1994: 652-657 |
| 4 | | Charles J. Alpert,
Andrew B. Kahng:
A general framework for vertex orderings, with applications to netlist clustering.
ICCAD 1994: 63-67 |
| 1993 |
|---|
| 3 | | Charles J. Alpert,
Andrew B. Kahng:
Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning.
DAC 1993: 743-748 |
| 2 | | Charles J. Alpert,
Jason Cong,
Andrew B. Kahng,
Gabriel Robins,
Majid Sarrafzadeh:
Minimum Density Interconneciton Trees.
ISCAS 1993: 1865-1868 |
| 1 | | Charles J. Alpert,
T. C. Hu,
Jen-Hsin Huang,
Andrew B. Kahng:
A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing.
ISCAS 1993: 1869-1872 |
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