A. E. A. Almaini

	2011
14		B. A. Al Jassani, N. Urquhart, A. E. A. Almaini: State assignment for sequential circuits using multi-objective genetic algorithm. IET Computers & Digital Techniques 5(4): 296-305 (2011)
13		Lun-Yao Wang, Yinshui Xia, Xiexiong Chen, A. E. A. Almaini: Reed-Muller function optimization techniques with onset table. Journal of Zhejiang University - Science C 12(4): 288-296 (2011)
	2010
12		B. A. Al Jassani, N. Urquhart, A. E. A. Almaini: Manipulation and optimisation techniques for Boolean logic. IET Computers & Digital Techniques 4(3): 227-239 (2010)
	2008
11		M. Yang, L. Wang, J. R. Tong, A. E. A. Almaini: Techniques for dual forms of Reed-Muller expansion conversion. Integration 41(1): 113-122 (2008)
	2006
10		M. Yang, L. Wang, A. E. A. Almaini: Fast Conversion for Large Canonical OR-Coincidence Functions. APCCAS 2006: 1643-1646
	2005
9		Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini: A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock. J. Comput. Sci. Technol. 20(2): 237-242 (2005)
	2004
8		B. Ali, A. E. A. Almaini, Tatiana Kalganova: Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits. Genetic Programming and Evolvable Machines 5(1): 11-29 (2004)
	2003
7		Yinshui Xia, B. Ali, A. E. A. Almaini: Area and power optimization of FPRM function based circuits. ISCAS (5) 2003: 329-332
6		Yinshui Xia, Xunwei Wu, A. E. A. Almaini: Power Minimization of FPRM Functions Based on Polarity Conversion. J. Comput. Sci. Technol. 18(3): 325-331 (2003)
	2002
5		Yinshui Xia, A. E. A. Almaini: Best Polarity for Low Power XOR Gate Decomposition. DSD 2002: 53-59
	2001
4		L. Wang, A. E. A. Almaini: Multilevel Logic Minimization Using Functional Don't Cares. VLSI Design 2001: 417-424
3		M. MacCallum, A. E. A. Almaini: The Application of the Wavelet Transform to Polysomnographic Signals. WAA 2001: 284-295
	1994
2		Z. Guan, P. Thomson, A. E. A. Almaini: A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter. ICCD 1994: 298-301
	1978
1		A. E. A. Almaini: Sequential Machine Implementations Using Universal Logic Modules. IEEE Trans. Computers 27(10): 951-960 (1978)

Coauthor Index

1	B. Ali	[7] [8]
2	Xiexiong Chen	[13]
3	Z. Guan	[2]
4	B. A. Al Jassani	[12] [14]
5	Tatiana Kalganova	[8]
6	M. MacCallum	[3]
7	P. Thomson	[2]
8	J. R. Tong	[11]
9	N. Urquhart	[12] [14]
10	L. Wang	[4] [10] [11]
11	Lun-Yao Wang	[9] [13]
12	Xunwei Wu	[6]
13	Yinshui Xia	[5] [6] [7] [9] [13]
14	M. Yang	[10] [11]

Colors in the list of coauthors

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