Mythri Alle

	2011
14		Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan: Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC 2011: 125-132
	2010
13		Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita: Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES 2010: 77-86
12		N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. ICSAMOS 2010: 178-184
11		Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS 2010: 265-272
10		Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI 2010: 161-166
	2009
9		Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan: Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC 2009: 204-215
8		Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, S. Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan: An Input Triggered Polymorphic ASIC for H.264 Decoding. ASAP 2009: 106-113
7		Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan: Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES 2009: 127-136
6		Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan: REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embedded Comput. Syst. 9(2): (2009)
	2008
5		Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan: Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP 2008: 13-18
4		Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan: RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP 2008: 251-256
3		Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan: Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP 2008: 287-292
	2007
2		A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL 2007: 558-561
	2006
1		Mythri Alle, Jayanta Biswas, S. K. Nandy: High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP 2006: 317-322

Coauthor Index

1	Jayanta Biswas	[1]
2	Prasenjit Biswas	[6] [7] [10] [11]
3	Jugantor Chetia	[6] [7]
4	Rajashekhar Chowhan	[8]
5	Saptarsi Das	[6] [7]
6	Avinaba Dutta	[12]
7	Alexander Fell	[4] [5] [6] [7] [9]
8	Masahiro Fujita	[13] [14]
9	Ganesh Garga	[13]
10	Ratna Krishnamoorthy	[13] [14]
11	Sravanthi Mantha	[8]
12	Rajdeep Mondal	[10]
13	S. K. Nandy (Soumitra Kumar Nandy)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
14	Ranjani Narayan	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
15	Joseph Nimmy	[4] [5] [6]
16	M. Prasadarao	[12]
17	N. Thambi Prashank	[12]
18	Ramesh C. Ramesh	[5]
19	Adarsha Rao	[3] [5] [6] [8]
20	C. Ramesh Reddy	[4] [6]
21	S. Sankaraiah	[8]
22	A. N. Satrawala	[2]
23	Reyaz Shaik	[8]
24	Pramod P. Udupa	[10]
25	Sainath V	[8]
26	Keshavan Varadarajan	[2] [4] [5] [6] [7] [9] [10] [11] [12] [13] [14]

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