Massimo Alioto

	2012
85		Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey: Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ISSCC 2012: 482-484
84		Massimo Alioto: Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial. IEEE Trans. on Circuits and Systems 59-I(1): 3-29 (2012)
	2011
83		Massimo Alioto: Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cells. ECCTD 2011: 536-539
82		Fabio Frustaci, Pasquale Corsonello, Massimo Alioto: Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. ECCTD 2011: 592-595
81		Milena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto: Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations. ISCAS 2011: 2043-2046
80		Fabio Frustaci, Pasquale Corsonello, Massimo Alioto: Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. ISCAS 2011: 2075-2078
79		Davide Baccarin, David Esseni, Massimo Alioto: A novel back-biasing low-leakage technique for FinFET forced stacks. ISCAS 2011: 2079-2082
78		Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jerome Mitard, Liesbeth Witters, Thomas Y. Hoffmann: Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. ISCAS 2011: 2249-2252
77		Massimo Alioto, Elio Consoli, Gaetano Palumbo: DET FF topologies: A detailed investigation in the energy-delay-area domain. ISCAS 2011: 563-566
76		Massimo Alioto, Elio Consoli, Gaetano Palumbo: Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. IEEE Trans. VLSI Syst. 19(5): 725-736 (2011)
75		Massimo Alioto, Elio Consoli, Gaetano Palumbo: Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. IEEE Trans. VLSI Syst. 19(5): 737-750 (2011)
74		Massimo Alioto: Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells. IEEE Trans. VLSI Syst. 19(5): 751-762 (2011)
73		Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer, Brice De Jaeger: Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements. IEEE Trans. VLSI Syst. 19(9): 1569-1582 (2011)
72		Fabio Frustaci, Massimo Alioto, Pasquale Corsonello: Tapered-Vth Approach for Energy-Efficient CMOS Buffers. IEEE Trans. on Circuits and Systems 58-I(11): 2698-2707 (2011)
71		Massimo Alioto, Gaetano Palumbo, Massimo Poli: Optimized design of parallel carry-select adders. Integration 44(1): 62-74 (2011)
70		Massimo Alioto: Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools. Microelectronics Journal 42(1): 63-73 (2011)
	2010
69		Massimo Alioto: Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits. ISCAS 2010: 1468-1471
68		Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer: Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits. ISCAS 2010: 1699-1702
67		Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto: Design metrics for RTL level estimation of delay variability due to intradie (random) variations. ISCAS 2010: 2498-2501
66		Massimo Alioto: Analysis of layout density in FinFET standard cells and impact of fin technology. ISCAS 2010: 3204-3207
65		Massimo Alioto, Elio Consoli, Gaetano Palumbo: Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. ISCAS 2010: 321-324
64		Massimo Alioto, Paolo Bennati, Roberto Giorgi: Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. ISCAS 2010: 37-40
63		Massimo Alioto, Elio Consoli, Gaetano Palumbo: Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. PATMOS 2010: 62-72
62		Massimo Alioto, Massimo Poli, Santina Rocchi: Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms. IEEE Trans. Dependable Sec. Comput. 7(3): 226-239 (2010)
61		Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi: Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology. IEEE Trans. VLSI Syst. 18(2): 232-245 (2010)
60		Massimo Alioto, Gaetano Palumbo, Melita Pennisi: Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. IEEE Trans. VLSI Syst. 18(5): 697-710 (2010)
59		Massimo Alioto, Massimo Poli, Santina Rocchi: A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits. IEEE Trans. VLSI Syst. 18(5): 711-724 (2010)
58		Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti: Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits. IEEE Trans. on Circuits and Systems 57-I(2): 355-367 (2010)
57		Massimo Alioto, Elio Consoli, Gaetano Palumbo: Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. IEEE Trans. on Circuits and Systems 57-I(6): 1273-1286 (2010)
56		Massimo Alioto, Elio Consoli, Gaetano Palumbo: General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. IEEE Trans. on Circuits and Systems 57-I(7): 1583-1596 (2010)
55		Massimo Alioto: Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis. IEEE Trans. on Circuits and Systems 57-I(7): 1597-1607 (2010)
54		Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy. Journal of Circuits, Systems, and Computers 19(4): 879-895 (2010)
53		Massimo Alioto, Stéphane Badel, Yusuf Leblebici: Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff. Microelectronics Journal 41(10): 669-679 (2010)
	2009
52		Massimo Alioto, Elio Consoli, Gaetano Palumbo: Optimum clock slope for flip-flops within a clock domain: Analysis and a case study. ICECS 2009: 275-278
51		Massimo Alioto, Gaetano Palumbo, Melita Pennisi: Analysis of the impact of random process variations in CMOS tapered buffers. ICECS 2009: 57-60
50		Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti: Leakage Power Analysis attacks: Theoretical analysis and impact of variations. ICECS 2009: 85-88
49		Massimo Alioto, Stéphane Badel, Yusuf Leblebici: Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. ISCAS 2009: 1285-1288
48		Massimo Alioto: Understanding Loading Effects of RC Uniform Interconnects. ISCAS 2009: 2269-2272
47		Massimo Alioto, Yusuf Leblebici: Analysis and Design of Ultra-low Power Subthreshold MCML Gates. ISCAS 2009: 2557-2560
46		Massimo Alioto, Elio Consoli, Gaetano Palumbo: Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. ISCAS 2009: 3150-3153
45		Massimo Alioto, Gaetano Palumbo, Massimo Poli: Analysis and Modeling of Energy Consumption in RLC Tree Circuits. IEEE Trans. VLSI Syst. 17(2): 278 (2009)
44		Armin Tajalli, Massimo Alioto, Yusuf Leblebici: Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. IEEE Trans. on Circuits and Systems 56-II(2): 127-131 (2009)
	2008
43		Massimo Alioto, Gaetano Palumbo: Power-delay optimization in MCML tapered buffers. ISCAS 2008: 141-144
42		Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer: Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148
41		Massimo Alioto, Luca Fondelli, Santina Rocchi: Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. ISCAS 2008: 1572-1575
40		Massimo Alioto, Massimo Poli, Gaetano Palumbo: Explicit energy evaluation in RLC tree circuits with ramp inputs. ISCAS 2008: 2865-2868
39		Massimo Alioto, Massimo Poli, Santina Rocchi: A general model for differential power analysis attacks to static logic circuits. ISCAS 2008: 3346-3349
38		Massimo Alioto, Gaetano Palumbo, Melita Pennisi: Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. PATMOS 2008: 136-145
37		Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici: Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS 2008: 21-30
36		Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi: Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. PATMOS 2008: 31-41
35		Massimo Alioto, Gaetano Palumbo: Power-Aware Design of Nanometer MCML Tapered Buffers. IEEE Trans. on Circuits and Systems 55-II(1): 16-20 (2008)
	2007
34		Massimo Alioto, Gaetano Palumbo: High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. ISCAS 2007: 2998-3001
33		Massimo Alioto, Gaetano Palumbo: Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. ISCAS 2007: 3255-3258
32		Massimo Alioto, Gaetano Palumbo: Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. ISCAS 2007: 3732-3735
31		Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. ISCAS 2007: 693-696
30		Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli: Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. ISCAS 2007: 861-864
29		Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo: Mixed Full Adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal 38(1): 130-139 (2007)
	2006
28		Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: A technique to design high entropy chaos-based true random bit generators. ISCAS 2006
27		Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli: Analysis and design of MCML gates with hysteresis. ISCAS 2006
26		Massimo Alioto, Gaetano Palumbo: Delay uncertainty due to supply variations in static and dynamic full adders. ISCAS 2006
25		Massimo Alioto, Gaetano Palumbo, Massimo Poli: Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. ISCAS 2006
24		Massimo Alioto, Gaetano Palumbo: Nanometer MCML gates: models and design considerations. ISCAS 2006
23		Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli: Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. PATMOS 2006: 593-602
22		Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli: Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. PATMOS 2006: 624-633
21		Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits. IEEE T. Instrumentation and Measurement 55(5): 1451-1458 (2006)
20		Massimo Alioto, Gaetano Palumbo: Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. IEEE Trans. VLSI Syst. 14(12): 1322-1335 (2006)
19		Massimo Alioto, Gaetano Palumbo, Massimo Poli: Energy Consumption in RC Tree Circuits. IEEE Trans. VLSI Syst. 14(5): 452-461 (2006)
	2005
18		Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: Long period pseudo random bit generators derived from a discretized chaotic map. ISCAS (2) 2005: 892-895
17		Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli: An approach to the design of PFSCL gates. ISCAS (3) 2005: 2437-2440
16		Massimo Alioto, Gaetano Palumbo: Design techniques for low-power cascaded CML gates. ISCAS (5) 2005: 4685-4688
15		Massimo Alioto, Gaetano Palumbo, Massimo Poli: Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. PATMOS 2005: 355-363
	2004
14		Massimo Alioto, Gaetano Palumbo, Massimo Poli: A gate-level strategy to design Carry Select Adders. ISCAS (2) 2004: 465-468
13		Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli: Positive-Feedback Source-Coupled Logic: a delay model. ISCAS (2) 2004: 641-644
12		Massimo Alioto, Gaetano Palumbo, Massimo Poli: Evaluation of energy consumption in RC ladder circuits driven by a ramp input. IEEE Trans. VLSI Syst. 12(10): 1094-1107 (2004)
	2003
11		Massimo Alioto, Gaetano Palumbo: Design of MUX, XOR and D-latch SCL gates. ISCAS (5) 2003: 261-264
10		Massimo Alioto, Rosario Mita, Gaetano Palumbo: Performance evaluation of the low-voltage CML D-latch topology. Integration 36(4): 191-209 (2003)
	2002
9		Massimo Alioto, Gaetano Palumbo: Power-delay trade-offs in SCL gates. ISCAS (3) 2002: 249-252
8		Massimo Alioto, Gaetano Palumbo, Massimo Poli: An Approach to Energy Consumption Modeling in RC Ladder Circuits. PATMOS 2002: 239-246
7		Massimo Alioto, Gaetano Palumbo: Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. PATMOS 2002: 429-437
6		Massimo Alioto, Gaetano Palumbo: Analysis and comparison on full adder block in submicron technology. IEEE Trans. VLSI Syst. 10(6): 806-823 (2002)
	2001
5		Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo: CML ring oscillators: oscillation frequency. ISCAS (4) 2001: 112-115
4		Massimo Alioto, Gaetano Palumbo: Power estimation in adiabatic circuits: a simple and accurate model. IEEE Trans. VLSI Syst. 9(5): 608-615 (2001)
	2000
3		Massimo Alioto, Gaetano Palumbo: Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. PATMOS 2000: 265-275
	1999
2		Massimo Alioto, Gaetano Palumbo: Highly accurate and simple models for CML and ECL gates. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1369-1375 (1999)
	1998
1		Massimo Alioto, Gaetano Palumbo: Novel Simple Models Of Cml Propagation Delay. Great Lakes Symposium on VLSI 1998: 270-274

Coauthor Index

1	Tommaso Addabbo	[18] [21] [28] [31] [54]
2	Matteo Agostinelli	[36] [61]
3	Davide Baccarin	[79]
4	Stéphane Badel	[49] [53]
5	Paolo Bennati	[64]
6	Elizabeth J. Brauer	[37] [42]
7	Giuseppe Di Cataldo	[5] [29]
8	Elio Consoli	[46] [52] [56] [57] [63] [65] [75] [76] [77] [85]
9	Pasquale Corsonello	[72] [80] [82]
10	Felice Crupi	[68] [73] [78]
11	Milena Djukanovic	[81]
12	David Esseni	[36] [61] [79]
13	Luca Fondelli	[41]
14	Ada Fort	[13] [17] [18] [21] [28] [31] [54]
15	Jacopo Franco	[78]
16	Fabio Frustaci	[72] [80] [82]
17	Luca Giancane	[50] [58] [81]
18	Roberto Giorgi	[64]
19	Guido Groeseneken	[78]
20	Frank K. Gürkaynak	[42]
21	Thomas Y. Hoffmann	[78]
22	Brice De Jaeger	[73]
23	Ben Kaczer	[68] [73] [78]
24	Yusuf Leblebici	[37] [42] [44] [47] [49] [53]
25	Paolo Magnone	[68] [73] [78]
26	Koushik Maharatna	[67]
27	Michael Merrett	[67]
28	Rosario Mita	[10]
29	Jerome Mitard	[78]
30	Gaetano Palumbo	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [19] [20] [24] [25] [26] [29] [32] [33] [34] [35] [38] [40] [43] [45] [46] [51] [52] [56] [57] [60] [63] [65] [71] [75] [76] [77] [85]
31	Luca Pancioni	[13] [17] [27]
32	Melita Pennisi	[38] [51] [60]
33	Massimo Poli	[8] [12] [14] [15] [19] [22] [23] [25] [30] [39] [40] [45] [59] [62] [71]
34	Jan M. Rabaey	[85]
35	Santina Rocchi	[13] [17] [18] [21] [22] [23] [27] [28] [30] [31] [39] [41] [54] [59] [62]
36	Giuseppe Scotti	[50] [58] [81]
37	Luca Selmi	[36] [61]
38	Armin Tajalli	[37] [42] [44]
39	Alessandro Trifiletti	[50] [58] [81]
40	Valerio Vignoli	[13] [17] [18] [21] [22] [23] [27] [28] [30] [31] [54]
41	Yangang Wang	[67]
42	Liesbeth Witters	[78]
43	Mark Zwolinski	[67]

Colors in the list of coauthors

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