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| 2005 | ||
|---|---|---|
| 1 | Syed Masood Ali, Rabin Raut, Mohamad Sawan: A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture. IWSOC 2005: 123-126 | |
| 1 | Rabin Raut | [1] |
| 2 | Mohamad Sawan | [1] |
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