Ignacio Algredo-Badillo

	2011
7		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD 2011: 543-549
	2010
6		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Computers & Electrical Engineering 36(3): 565-577 (2010)
5		Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo: A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. Journal of Circuits, Systems, and Computers 19(2): 425-433 (2010)
	2009
4		Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo: An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. Computers & Electrical Engineering 35(1): 54-58 (2009)
	2008
3		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig 2008: 421-426
2		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval: Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Transactions 91-D(10): 2519-2523 (2008)
	2006
1		Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido: Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) 2006: 456-465

Coauthor Index

1	René Cumplido (René Cumplido-Parra)	[1] [2] [3] [4] [5] [6] [7]
2	Miguel Morales-Sandoval	[2] [3] [4] [5] [6] [7]
3	Claudia Feregrino Uribe (Claudia Feregrino)	[1] [2] [3] [4] [5] [6] [7]

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