 | 2006 |
|---|
| 5 |       | Jaafar Alghazo:
Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs.
CDES 2006: 39-45 |
| 2005 |
|---|
| 4 | | Jaafar Alghazo,
Nazeih Botros:
Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs.
CDES 2005: 136-142 |
| 2004 |
|---|
| 3 |  | Adil Akaaboune,
Nazeih Botros,
Jaafar Alghazo:
Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design.
MTDT 2004: 13-18 |
| 2 | | Jaafar Alghazo,
Adil Akaaboune,
Nazeih Botros:
SF-LRU Cache Replacement Algorithm.
MTDT 2004: 19-24 |
| 2003 |
|---|
| 1 | | Nazeih Botros,
Adil Akaaboune,
Jaafar Alghazo:
Modeling and Realization of the Human Growth Hormone Secretion Mechanism using VHDL and FPGAs.
Modelling, Simulation, and Optimization 2003: 13-18 |
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